Organic light emitting display and driving method thereof

Patent metadata

Field	Value
Publication number	US-9990883-B2
Application number	US-201615226047-A
Country	US
Kind code	B2
Filing date	Aug 2, 2016
Priority date	Aug 31, 2015
Publication date	Jun 5, 2018
Grant date	Jun 5, 2018

Abstract

An organic light emitting display comprises a display panel having data lines, scan lines, emission signal lines, and pixels. The display also comprises a data driver configured to provide a data voltage corresponding to an input image to one of the data lines connected to a pixel and a gate driver configured to provide an N-th scan pulse to an N-th scan line to charge the pixel with the data voltage during a scan period within a frame period. The display further comprises an emission driver configured to receives shift clocks and the N-th scan pulse from the gate driver to provide an N-th emission control signal to the N-th emission signal line and to control a current path through the OLED based on the N-th emission control signal during a duty driving period following the scan period within a frame period.

First claim

What is claimed is:

1. An organic light emitting display, comprising:
a display panel having a plurality of data lines, a plurality of scan lines crossing the data lines, a plurality of emission signal lines, and a pixel connected to an N-th scan line and an N-th emission signal line, where N is a positive integer, the pixel including:
an organic light emitting diode (OLED); and
a first pixel TFT connected to the OLED and configured to control an amount of current to flow through the OLED based on a voltage between a gate and a source of the first pixel TFT;

a data driver configured to provide a data voltage corresponding to an input image to one of the data lines connected to the pixel;
a gate driver configured to provide an N-th scan pulse to the N-th scan line to charge the pixel with the data voltage during a scan period within a frame period; and
an emission driver configured to receives shift clocks and the N-th scan pulse from the gate driver to provide an N-th emission control signal to the N-th emission signal line and to control a current path through the OLED based on the N-th emission control signal during a duty driving period following the scan period within the frame period,
wherein the voltage between the gate and the source of the first pixel TFT is configured to remain substantially constant during the duty driving period,
wherein the emission driver includes a shift register comprising:
an output node configured to output the N-th emission control signal;
a Q node and a QB node;
a pull-up transistor having a gate connected to the Q node and a source connected to the output node, and configured to charge the output node to a high-potential driving voltage to set the N-th emission control signal to an ON level based on a voltage at the Q node;
a capacitor connected between the gate and the source of the pull-up transistor;
a pull-down transistor configured to discharge the output node to a base voltage to set the N-th emission control signal to an OFF level based on a voltage at the QB node;
a first TFT and a second TFT configured to charge the Q node to the ON level base on a first shift clock and a (N−1)-th emission control signal;
a third TFT configured to charge the QB node to a reset signal based on the N-th scan pulse;
a fourth TFT configured to charge a node between two TFTs in the pull-down transistor to the high-potential driving voltage;
a fifth TFT configured to charge the QB node based on a (N−1)-th scan pulse from the gate driver and a second shift clock;
a sixth TFT configured to discharge the Q node to the base voltage based on the voltage at the QB node; and
a seventh TFT configured to discharge the QB node to the base voltage based on the first shift clock.

2. The display of claim 1 , wherein each of the first shift clock and the second shift clock is configured as a pair of clock pulses, and
wherein the pair of clock pulses of the first shift clock does not overlap the pair of clock pulses of the second shift clock.

3. The display of claim 1 , wherein the N-th emission control signal is a pulse width modulated signal configured to swing between an OFF level and an ON level according to a duty ratio, and
wherein the N-th emission control signal switches from the OFF level to the ON level at least twice during the duty driving period.

4. The display of claim 3 , wherein the N-th scan pulse includes a first scan pulse and a second scan pulse,
wherein the pixel further includes:
a storage capacitor connected between the gate and the source of the first pixel TFT; and
a second pixel TFT connected between a high-potential driving voltage line and the first pixel TFT, and configured to turn on or off based on the N-th emission control signal to control the current path through the OLED, and

wherein the second pixel TFT is configured to turn off at least once based on the N-th emission control signal being at the OFF level to block the current path through the OLED at least once during the duty driving period, and the voltage between the gate and the source of the first pixel TFT remains substantially constant regardless of whether the second pixel TFT is turned on or off.

5. The display of claim 4 , wherein the pixel further includes:
a third pixel TFT configured to supply a reference voltage or the data voltage to the gate of the first pixel TFT based on the first scan pulse during the scan period and to be turned off during the duty driving period; and
a fourth pixel TFT configured to supply a predetermined initial voltage to the source of the first pixel TFT base on the second scan pulse.

6. An organic light emitting display, comprising:
a display panel having a plurality of data lines, a plurality of scan lines crossing the data lines, a plurality of emission signal lines, and a pixel connected to an N-th scan line and an N-th emission signal line, where N is a positive integer;
a timing controller configured to receive an input image data and timing signals from a host system, and to output a data timing control signal, a gate timing control signal, and a plurality of duty timing control signals;
a data driver configured to provide a data voltage corresponding to the input image data to one of the data lines connected to the pixel based on the data timing control signal;
a gate driver configured to provide a data-writing scan pulse to the N-th scan line based on the gate timing control signal to charge the pixel with the data voltage during a scan period within a frame period; and
an emission driver configured to generate an N-th scan pulse independently of the gate driver, and to provide an N-th emission control signal to the N-th emission signal line based on the N-th scan pulse and at least one of the duty timing control signals, during a duty driving period following the scan period within the frame period,
wherein the emission driver includes:
a first shift register configured to generate the N-th scan pulse based on a first set of shift clocks;
a second shift register configured to generate an N-th duty signal based on a second set of shift clocks; and
a third shift register configured to receive the N-th scan pulse and the N-th duty signal, and to output the N-th emission control signal based on the N-th scan pulse, the N-th duty signal, and a third set of shift clocks, and

wherein the duty timing control signals include one or more shift clocks in the first to the third sets of shift clocks.

7. The display of claim 6 , wherein the third shift register includes:
an output node configured to output the N-th emission control signal;
a Q node and a QB node;
a pull-up transistor having a gate connected to the Q node and a source connected to the output node, and configured to charge the output node to a high-potential driving voltage to set the N-th emission control signal to an ON level based on a voltage at the Q node;
a capacitor connected between the gate and the source of the pull-up transistor; and
a pull-down transistor configured to discharge the output node to a base voltage to set the N-th emission control signal to an OFF level based on a voltage at the QB node.

8. The display of claim 7 , wherein:
the first shift register is further configured to generate an (N−1)-th scan pulse based on the first set of shift clocks;
the third set of shift clocks include a first shift clock and a second shift clock; and
the third shift register is further configured to output an (N−1)-th emission control signal to an (N−1)-th emission signal line, and to receive a reset signal from the timing controller, the third shift register further including:
a first TFT and a second TFT configured to charge the Q node to the ON level base on the first shift clock and the (

Assignees

• Lg Display Co Ltd

Inventors

• Park Youngju
• Yoon Sungwook
• Na Sehwan

Classifications

• G09G2310/0251

  Precharge or discharge of pixel before applying new pixel voltage · CPC title

• G09G2300/0852

  being a dynamic memory with more than one capacitor · CPC title

• G09G2310/0262

  The addressing of the pixel, in a display other than an active matrix LCD, involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependent on signals of two data electrodes · CPC title

• G09G3/3266

  Details of drivers for scan electrodes · CPC title

• G09G3/3233 Primary

  with pixel circuitry controlling the current through the light-emitting element · CPC title