Calibration scheme for a non-linear ADC

Patent metadata

Field	Value
Publication number	US-12525985-B2
Application number	US-202418440113-A
Country	US
Kind code	B2
Filing date	Feb 13, 2024
Priority date	Jan 12, 2021
Publication date	Jan 13, 2026
Grant date	Jan 13, 2026

Abstract

In described examples, an analog to digital converter (ADC), having an input operable to receive an analog signal and an output operable to output a digital representation of the analog signal, includes a voltage to delay (VD) block. The VD block is coupled to the input of the ADC and generates a delay signal responsive to a calibration signal. A backend ADC is coupled to the VD block, and receives the delay signal. The backend ADC having multiple stages including a first stage. A calibration engine is coupled to the multiple stages and the VD block. The calibration engine measures an error count of the first stage and stores a delay value of the first stage for which the error count is minimum.

First claim

What is claimed is:

1 . An analog to digital converter (ADC) comprising:
a first ADC having a first stage including a first delay block; and a first circuit coupled to the first ADC and configured to generate a plurality of input codes; wherein the first delay block is configured to generate a digital code in response to the plurality of input codes, and the first circuit is configured to determine an error count responsive to the digital code and configured to modify a delay value of the first delay block based on the error count.

2 . The ADC of claim 1 , wherein the first ADC includes a plurality of stages including the first stage, and each stage of the plurality of stages further comprises:
a delay block coupled to the first circuit; a logic gate coupled to the delay block; and a delay comparator coupled to the delay block and the first circuit.

3 . The ADC of claim 1 further comprising:
a DAC (digital to analog converter) coupled to the first circuit, the DAC configured to generate a calibration signal in response to an input code of the plurality of input codes;
a multiplexer coupled to the DAC, and configured to receive an input voltage and the calibration signal;
a voltage to delay (VD) block coupled to the multiplexer; and
a storage circuit coupled to the first ADC.

4 . The ADC of claim 3 configured to operate in a delay-calibration mode, a memory-calibration mode, and a mission mode, wherein the delay-calibration mode includes a plurality of cycles, and in a cycle of the plurality of cycles:
the first circuit is configured to modify the delay value of the first delay block in the first stage;
the first circuit is configured to generate the plurality of input codes;
the VD block is configured to generate a plurality of delay signals in response to the plurality of input codes;
the first stage is configured to generate the digital code in response to the plurality of delay signals; and
the first circuit is configured to determine the error count responsive to the digital code, in which the error count is an absolute difference in a number of ones and zeroes in the digital code.

5 . The ADC of claim 4 , wherein the delay value for which the error count of the first delay block is minimum is stored as the delay value of the first delay block.

6 . The ADC of claim 5 further comprising a second stage in the first ADC, the second stage is coupled to the first stage, and configured to receive an output of the first stage, wherein in the delay-calibration mode:
the first circuit is configured to modify a delay value of a second delay block in the second stage;
the first circuit is configured to generate the plurality of input codes;
the VD block is configured to generate the plurality of delay signals in response to the plurality of input codes;
the second stage is configured to generate a digital code in response to the plurality of delay signals; and
the first circuit is configured to determine the error count responsive to the digital code, in which the error count is the absolute difference in a number of ones and zeroes in the digital code.

7 . The ADC of claim 6 , wherein the delay value for which the error count of the second delay block is minimum is stored as the delay value of the second delay block.

8 . The ADC of claim 4 , wherein in the memory-calibration mode:
the first circuit is configured to generate a plurality of input codes; the DAC is configured to generate a calibration signal in response to an input code of the plurality of input codes; the VD block is configured to generate a delay signal responsive to the calibration signal; the first ADC is configured to generate an output code responsive to the delay signal; and the storage circuit is configured to store the input code at an address corresponding to the output code.

9 . The ADC of claim 4 , wherein the VD block further comprising:
one or more preamplifiers, each preamplifier configured to compare one of the input voltage and the calibration signal to a threshold voltage; and a delay multiplexer coupled to the one or more preamplifiers, and configured to generate a delay signal based on an output of one of the preamplifiers.

10 . The ADC of claim 4 , wherein in the mission mode:
the VD block is configured to generate a delay signal in response to an input voltage; and the first ADC is configured to generate a raw code in response to the delay signal, wherein the input code stored at an address corresponding to the raw code is generated as a final output.

11 . A method of operating an analog to digital converter (ADC) comprising:
generating a plurality of input codes by a first circuit; generating a digital code by a first delay block in response to the plurality of input codes; determining an error count responsive to the digital code; and modifying a delay value of the first delay block based on the error count.

12 . The method of claim 11 further comprising:
generating a calibration signal in response to an input code of the plurality of input codes;
generating a delay signal responsive to the calibration signal; and
providing the delay signal to a first ADC, the first ADC having a plurality of stages including a first stage, the first stage having the first delay block.

13 . The method of claim 12 further comprising operating the ADC in a delay-calibration mode, a memory-calibration mode, and a mission mode, wherein the delay-calibration mode includes a plurality of cycles, and in a cycle of the plurality of cycles:
modifying the delay value of the first delay block in the first stage;
generating the plurality of input codes by the first circuit;
generating a plurality of delay signals in response to the plurality of input codes;
generating the digital code by the first delay block in response to the plurality of delay signals; and
determining the error count responsive to the digital code, in which the error count is an absolute difference in a number of ones and zeroes in the digital code.

14 . The method of claim 13 further comprising storing the delay value for which the error count is minimum as the delay value of the first delay block in the first stage.

15 . The method of claim 13 further comprising providing an output of the first stage to a second stage, wherein in the delay-calibration mode:
modifying a delay value of a second delay block in the second stage;
generating the plurality of input codes by the first circuit;
generating the plurality of delay signals in response to the plurality of input codes;
generating a digital code by the second delay block in response to the plurality of delay signals; and
determining the error count responsive to the digital code, in which the error count is the absolute difference in a number of ones and zeroes in the digital code.

16 . The method of claim 15 further comprising storing the delay value for which the error count is minimum as the delay value of the second delay block in the second stage.

17 . The method of claim 13 , wherein in the memory-calibration mode:
generating a plurality of input codes by the first circuit; generating a calibration signal in response to an input code of the plurality of input codes; generating a delay signal responsive to the calibration signal; generating an output code responsive to the delay signal; and storing the input code at an address corresponding to the output code.

18 . The method of claim 13 , wherein in the mission mode:
generating a delay signal in re

Assignees

• Texas Instruments Inc

Inventors

• Varshney Himanshu
• Nagarajan Viswanathan
• Babu Charls
• Rajagopal Narasimhan
• Miglani Eeshan
• Pentakota Visvesvaraya A

Classifications

• H03M1/06

  Continuously compensating for, or preventing, undesired influence of physical parameters (periodically, {e.g. by using stored correction values,} H03M1/10) · CPC title

• H03M1/10

  Calibration or testing · CPC title

• H03M1/12

  Analogue/digital converters ({H03M1/001 – } H03M1/10 take precedence) · CPC title

• H03M1/002

  Provisions or arrangements for saving power, e.g. by allowing a sleep mode, using lower supply voltage for downstream stages, using multiple clock domains or by selectively turning on stages when needed · CPC title

• G04F10/005

  Time-to-digital converters [TDC] (analog-to-digital converters with intermediate conversion to time or phase H03M1/50, H03M1/60) · CPC title