Efficient calibration of errors in multi-stage analog-to-digital converter

Patent metadata

Field	Value
Publication number	US-9503116-B2
Application number	US-201514955916-A
Country	US
Kind code	B2
Filing date	Dec 1, 2015
Priority date	Dec 17, 2014
Publication date	Nov 22, 2016
Grant date	Nov 22, 2016

Abstract

Analog-to-digital converters (ADCs) can have errors which can affect their performance. To improve the performance, many techniques have been used to compensate or correct for the errors. When the ADCs are being implemented with sub-micron technology, ADCs can be readily and easily equipped with an on-chip microprocessor for performing a variety of digital functions. The on-chip microprocessor and any suitable digital circuitry can implement functions for reducing those errors, enabling certain undesirable artifacts to be reduced, and providing a flexible platform for a highly configurable ADC. The on-chip microprocessor is particularly useful for a randomized time-interleaved ADC. Moreover, a randomly sampling ADC can be added in parallel to a main ADC for calibration purposes. Furthermore, the overall system can include an efficient implementation for correcting errors in an ADC.

First claim

What is claimed is:

1. A multi-stage analog-to-digital converter with digitally assisted calibration, the multi-stage analog-to-digital converter comprising:
analog-to-digital converter stages in cascade, each analog-to-digital converter stage for generating a respective output code and a respective amplified output residue signal;
wherein for each analog-to-digital converter stage, the multi-stage analog-to-digital converter further comprises:
a dedicated memory element for st…

Assignees

• Analog Devices Inc

Inventors

• Speir Carroll C
• Otte Eric
• Bray Jeffrey Paul

Classifications

• H03M1/128 Primary

  Electricity · mapped topic

• H03M1/121

  Electricity · mapped topic

• H03M3/382

  Electricity · mapped topic

• H03M3/498

  Electricity · mapped topic

• H03M1/12

  Electricity · mapped topic