High-speed comparator for analog-to-digital converter

Patent metadata

Field	Value
Publication number	US-9455695-B2
Application number	US-201514834871-A
Country	US
Kind code	B2
Filing date	Aug 25, 2015
Priority date	Aug 29, 2014
Publication date	Sep 27, 2016
Grant date	Sep 27, 2016

Abstract

A comparator for an analog-to-digital converter is provided. The comparator includes a differential amplifier unit that receives a sampling signal and provides an output signal, based on a voltage provided by the sampling signal. The differential amplifier unit includes an input stage that receives the sampling signal and integrates a current on the integration nodes based on potentials of the sampling signal. The comparator includes a sense amplifier coupled with the integration nodes that detects a potential difference and amplifies the potential difference to generate the output signal. The comparator includes a charge injection circuit ( 30 ) to inject equal charges into the integration nodes.

First claim

What is claimed is:

1. An analog-to-digital comparator, comprising:
a differential amplifier unit wherein the differential amplifier unit receives a sampling signal and provides an output signal based on a voltage provided by the sampling signal, wherein the differential amplifier unit includes:
an input stage wherein the input stage receives the sampling signal and integrates a current on integration nodes based on potentials of the sampling signal;
a sense amplifier coupled with the integration nodes wherein the sense amplifier detects a potential difference and amplifies the potential difference to generate the output signal; and
a charge injection circuit wherein the charge injection circuit comprises injection capacitors each of which is coupled with a respective one of the integration nodes, so that charges are selectively injected into the integration nodes, and wherein each of the injection capacitors of the charge injection circuit is coupled with one first terminal thereof with a respective one of the integration nodes, wherein by changing a potential on a second terminal of the injection capacitors during the integration cycle charges are injected into the integration nodes, and wherein the charge injection circuit injects equal charges into the integration nodes.

2. The comparator according to claim 1 , wherein the sense amplifier includes cross-coupled inverters.

3. The comparator according to claim 2 , wherein one terminal of each of the cross-coupled inverters is coupled with a respective one of the integration nodes, so that the voltage over the cross-coupled inverters depends on the potential on the respective integration node.

4. The comparator according to claim 3 , wherein charges are selectively injected into the integration nodes before the voltage over the cross-coupled inverters reaches a value at which the sense amplifier becomes operational.

5. The comparator according to claim 1 , wherein the differential amplifier unit is configured to be operated in a regeneration cycle and an integration cycle according to a provided clock signal, wherein in the regeneration cycle the differential amplifier unit is deactivated and the integration nodes are charged with a predefined reference potential and wherein in the integration cycle the differential amplifier unit is activated and charges are injected into the integration nodes.

6. The comparator according to claim 1 , wherein the alteration of the potential on the second terminal of the injection capacitors is caused by the clock signal or a delayed further clock signal.

7. The comparator according to claim 1 , wherein the alteration of the potential on the second terminal of the injection capacitors is provided by an output of an inverter associated with each of the injection capacitors.

8. The comparator according to claim 7 , wherein the input of each of the inverters coupled with a respective one of the injection capacitors is either coupled with an inverted clock signal or with the integration node associated with the respective other of the injection capacitors, so that the potential change on the integration node is controlled by the potential change of the respective other integration node.

9. The comparator according to claim 1 , wherein the charge injection circuit is configured to be selectively enabled by a provided enable signal, so that charges are injected into the integration nodes depending on the enable signal.

Assignees

• IBM

Inventors

• Kull Lukas
• Toifl Thomas H

Classifications

• H03K5/249 Primary

  using clock signals · CPC title

• H03M1/44

  Sequential comparisons in series-connected stages with change in value of analogue signal · CPC title

• H03M1/466

  using switched capacitors · CPC title

• H03M1/403

  using switched capacitors · CPC title

• H03M1/002

  Provisions or arrangements for saving power, e.g. by allowing a sleep mode, using lower supply voltage for downstream stages, using multiple clock domains or by selectively turning on stages when needed · CPC title