Clock generation circuit, successive comparison A/D converter, and integrated circuit device

Patent metadata

Field	Value
Publication number	US-9369137-B2
Application number	US-201514880927-A
Country	US
Kind code	B2
Filing date	Oct 12, 2015
Priority date	Nov 4, 2014
Publication date	Jun 14, 2016
Grant date	Jun 14, 2016

Abstract

A clock generation circuit includes a first loop circuit configured to generate a first clock, and a second loop circuit configured to generate a second clock including a period different from a period of the first clock. A fluctuation in an amount of delay of the first clock is adjusted based on the second clock and the first clock including the period adjusted is output.

First claim

What is claimed is:

1. A clock generation circuit comprising:
a first loop circuit configured to generate a first clock; and
a second loop circuit configured to generate a second clock including a period different from a period of the first clock, wherein
a fluctuation in an amount of delay of the first clock is adjusted based on the second clock and the first clock including the period adjusted is output.

2. The clock generation circuit as claimed in claim 1 , wherein
the first loop circuit includes:
a first delay amount variable circuit configured to control the amount of delay of the first clock; and
a delay adjustment amount calculation circuit configured to receive the first clock and the second clock, and output a delay amount adjustment code for controlling the first delay amount variable circuit, and

the second loop circuit includes:
a first fixed delay circuit configured to apply a fixed amount of delay to the second clock; and
a second delay amount variable circuit configured to control an amount of delay of the second clock, based on the delay amount adjustment code.

3. The clock generation circuit as claimed in claim 2 , wherein
the first fixed delay circuit is controlled in an amount of delay by a fixed delay code fixed during an operation of the clock generation circuit, and
the fixed delay code is set larger than one code of the delay amount adjustment code.

4. The clock generation circuit as claimed in claim 2 , wherein
when the amount of delay of the first clock is decreased, the delay adjustment amount calculation circuit is configured to output the delay amount adjustment code to increase the amount of delay of the first clock, based on the second clock.

5. The clock generation circuit as claimed in claim 4 , wherein
the delay adjustment amount calculation circuit is configured to count edges of the first clock, and
when an edge count value in a first period is larger than a first count value, the delay adjustment amount calculation circuit is configured to determine that the amount of delay of the first clock is decreased.

6. The clock generation circuit as claimed in claim 1 , wherein
the first loop circuit includes:
a second fixed delay circuit configured to apply a fixed amount of delay to the first clock;
a first delay amount variable circuit configured to control the amount of delay of the first clock; and
a delay adjustment amount calculation circuit configured to receive the first clock and the second clock, and output a delay amount adjustment code for controlling the first delay amount variable circuit, and

the second loop circuit includes:
a second delay amount variable circuit configured to control an amount of delay of the second clock, based on the delay amount adjustment code.

7. The clock generation circuit as claimed in claim 6 , wherein
the second fixed delay circuit is controlled in an amount of delay by a fixed delay code fixed during a circuit operation, and
the fixed delay code is set larger than one code of the delay amount adjustment code.

8. The clock generation circuit as claimed in claim 6 , wherein
when the amount of delay of the first clock is increased, the delay adjustment amount calculation circuit is configured to output the delay amount adjustment code to decrease the amount of delay of the first clock, based on the second clock.

9. The clock generation circuit as claimed in claim 8 , wherein
the delay adjustment amount calculation circuit is configured to count edges of the first clock, and
when an edge count value in a first period is smaller than a first count value, the delay adjustment amount calculation circuit is configured to determine that the amount of delay of the first clock is increased.

10. The clock generation circuit as claimed in claim 1 , wherein
the first loop circuit includes:
a third fixed delay circuit configured to apply a fixed amount of delay to the first clock;
a first delay amount variable circuit configured to control the amount of delay of the first clock; and
a delay adjustment amount calculation circuit configured to receive the first clock and the second clock, and output a delay amount adjustment code for controlling the first delay amount variable circuit,

the second clock includes a first sub-clock and a second sub-clock,
the second loop circuit includes:
a first sub-loop circuit configured to generate the first sub-clock; and
a second sub-loop circuit configured to generate the second sub-clock,

the first sub-loop circuit includes:
a fourth fixed delay circuit configured to apply a fixed amount of delay to the first sub-clock; and
a first sub-delay amount variable circuit configured to control an amount of delay of the first sub-clock, based on the delay amount adjustment code, and
the second sub-loop circuit includes a second sub-delay amount variable circuit configured to control an amount of delay of the second sub-clock, based on the delay amount adjustment code.

11. The clock generation circuit as claimed in claim 10 , wherein
the fourth fixed delay circuit and the third fixed delay circuit are controlled in amount of delay by a fixed delay code fixed during an operation of the clock generation circuit, so that the amount of delay of the fourth fixed delay circuit becomes twice the amount of delay of the third fixed delay circuit, and
the fixed delay code is set larger than one code of the delay amount adjustment code.

12. The clock generation circuit as claimed in claim 10 , wherein
when the amount of delay of the first clock is decreased, the delay adjustment amount calculation circuit is configured to output the delay amount adjustment code to increase an amount of delay of the first clock, based on the first sub-clock, and
when the amount of delay of the first clock is increased, the delay adjustment amount calculation circuit is configured to output the delay amount adjustment code to decrease the amount of delay of the first clock, based on the second sub-clock.

13. The clock generation circuit as claimed in claim 12 , wherein
the delay adjustment amount calculation circuit is configured to count edges of the first clock,
when an edge count value in a first period is larger than a first count value, the delay adjustment amount calculation circuit is configured to determine that the amount of delay of the first clock is decreased, and
when the edge count value in the first period is become smaller than the first count value, the delay adjustment amount calculation circuit is configured to determine that the amount of delay of the first clock is increased.

14. A successive comparison A/D converter comprising:
a DAC configured to generate an analog voltage based on a digital code;
a comparator configured to perform a comparison operation using, as an input, the analog voltage generated by the DAC;
a DAC control circuit configured to successively change the digital code, based on an output of the comparator, and output a digital output obtained by digitally converting the analog voltage; and
a clock generation circuit configured to generate a first clock for controlling the comparison operation of the comparator, wherein
the clock generation circuit includes:
a first loop circuit configured to generate the first clock; and
a second loop circuit configured to generate a second clock including a period different from a period of the first clock, wherein
a fluctuation in an amount of delay of the first clock is adjusted based on the second clock and the first clock including the period adjusted is output.

15. The successive compariso

Assignees

• Socionext Inc

Inventors

• Masuko Shuichi

Classifications

• H03M1/46

  with digital/analogue converter for supplying reference values to converter · CPC title

• H03M1/0624

  by synchronisation · CPC title

• H03L7/0818 Primary

  the controlled phase shifter comprising coarse and fine delay or phase-shifting means · CPC title

• H03M1/468

  in which the input S/H circuit is merged with the feedback DAC array · CPC title

• H03M1/125

  Asynchronous, i.e. free-running operation within each conversion cycle · CPC title