Calibration technique for current steering DAC

Patent metadata

Field	Value
Publication number	US-9548752-B1
Application number	US-201615048027-A
Country	US
Kind code	B1
Filing date	Feb 19, 2016
Priority date	Aug 6, 2015
Publication date	Jan 17, 2017
Grant date	Jan 17, 2017

Abstract

The disclosure provides a current steering digital to analog converter (DAC) that includes a plurality of DAC elements. At least one DAC element of the plurality of DAC elements is coupled to a calibration circuit. The calibration circuit includes a fixed current source coupled to a primary node of the DAC element through a first estimation switch. A digital code generator is coupled to the primary node, and generates a first digital code corresponding to a primary voltage generated at the primary node. The digital code generator generates a second digital code. A correction DAC is coupled to the digital code generator and generates a bias voltage based on the second digital code. The bias voltage is provided to the DAC element such that a current flowing through each DAC element of the plurality of DAC elements is equal.

First claim

What is claimed is:

1. A current steering digital to analog converter (DAC) comprising:
a plurality of DAC elements, at least one DAC element of the plurality of DAC elements coupled to a calibration circuit, the calibration circuit comprising:
a fixed current source coupled to a primary node of the DAC element through a first estimation switch;
a digital code generator coupled to the primary node, and configured to generate a first digital code corresponding to a primary voltage generated at the primary node, the digital code generator configured to generate a second digital code; and
a correction DAC coupled to the digital code generator and configured to generate a bias voltage based on the second digital code, the bias voltage is provided to the DAC element such that a current flowing through each DAC element of the plurality of DAC elements is equal.

2. The current steering DAC of claim 1 , wherein each DAC element of the plurality of DAC element comprises:
a first resistor and a second resistor coupled to a power source;
a first switch coupled to the first resistor, and a second switch coupled to the second resistor, the first switch and the second switch are configured to be activated based on a digital input; and
a current source coupled to the first switch and the second switch, the current source comprising:
a transistor coupled between the first switch and the primary node, the transistor configured to receive the bias voltage from the correction DAC through a correction switch and the transistor coupled to a ground terminal through a second estimation switch; and
a degeneration resistor coupled between the primary node and the ground terminal.

3. The current steering DAC of claim 1 , wherein the digital code generator comprises:
an analog to digital converter (ADC) coupled to the primary node and configured to receive a first reference voltage; and
a digital engine coupled to the ADC and the correction DAC.

4. The current steering DAC of claim 3 , wherein the calibration circuit is configured to operate in an estimation mode and a correction mode, wherein in the estimation mode:
the first estimation switch and the second estimation switch are configured to be activated, and the correction switch is configured to be inactivated;
the ADC is configured to generate the first digital code corresponding to the primary voltage at the primary node; and
the digital engine is configured to store the first digital code.

5. The current steering DAC of claim 4 , wherein the correction mode comprises a plurality of correction cycles, one correction cycle of the plurality of correction cycle comprises:
the first estimation switch and the second estimation switch are configured to be inactivated, and the correction switch is configured to be activated;
the digital engine is configured to generate the second digital code;
the correction DAC is configured to generate the bias voltage based on the second digital code, wherein a new primary voltage is generated at the primary node when the bias voltage is provided to the DAC element; and
the ADC is configured to generate a third digital code corresponding to the new primary voltage generated at the primary node.

6. The current steering DAC of claim 5 , wherein after the plurality of correction cycles the third digital code is equal to the first digital code, and the digital engine is configured to store the second digital code for which the third digital code is equal to the first digital code.

7. The current steering DAC of claim 1 , wherein the digital code generator comprises:
a comparator coupled to the primary node, the comparator configured to compare the primary voltage and a second reference voltage to generate the first digital code;
a digital engine coupled to the comparator and configured to store the first digital code; and
an estimation DAC coupled to the digital engine, and configured to generate the second reference voltage.

8. The current steering DAC of claim 7 , wherein the estimation DAC further comprises:
a primary resistive ladder coupled between a first input voltage and the ground terminal, the primary resistive ladder having a plurality of resistors with voltage taps between two successive resistors of the plurality of resistors; and
a primary multiplexer coupled to the primary resistive ladder, and configured to generate the second reference voltage.

9. The current steering DAC of claim 1 , wherein the correction DAC comprises:
a secondary resistive ladder coupled between a second input voltage and the ground terminal, the secondary resistive ladder having a plurality of resistors with voltage taps between two successive resistors of the plurality of resistors; and
a secondary multiplexer coupled to the secondary resistive ladder, and configured to provide the bias voltage to the transistor through the correction switch.

10. A current steering DAC comprising:
a plurality of current sources, at least one current source comprising:
a transistor coupled between a first switch and a primary node; and
a degeneration resistor coupled between the primary node and a ground terminal;

a calibration circuit coupled to at least one current source of the plurality of current sources, the calibration circuit comprising:
a fixed current source coupled to the primary node through a first estimation switch; and
a digital code generator coupled to the primary node, and configured to generate a first digital code corresponding to a primary voltage generated at the primary node.

11. The current steering DAC of claim 10 , wherein the digital code generator comprises:
an analog to digital converter (ADC) coupled to the primary node and configured to receive a first reference voltage; and
a digital engine coupled to the ADC.

12. The current steering DAC of claim 10 , wherein the digital code generator comprises:
a comparator coupled to the primary node, the comparator configured to compare the primary voltage and a second reference voltage to generate the first digital code;
a digital engine coupled to the comparator and configured to store the first digital code; and
an estimation DAC coupled to the digital engine, and configured to generate the second reference voltage.

13. The current steering DAC of claim 10 further comprising a correction DAC coupled to the digital code generator and configured to provide a bias voltage to the current source based on a second digital code such that a current flowing through each current source of the plurality of current sources is equal.

14. The current steering DAC of claim 10 , wherein:
the transistor is configured to receive the bias voltage from the correction DAC through a correction switch and the transistor is coupled to the ground terminal through a second estimation switch.

15. A method of estimating mismatch in a plurality of current sources in a current steering DAC, the method comprising:
inactivating a transistor of a current source of the plurality of current sources, the transistor is coupled to a primary node of the current source;
generating a primary voltage at the primary node of the current source by coupling the primary node to a fixed current source;
generating a first digital code corresponding to a primary voltage;
generating a second digital code;
generating a bias voltage based on the second digital code; and
providing the bias voltage to the transistor such that a current flowing through each current source of the plurality of current sources is equal.

16. The method of claim 15 , wherein generating the first digita

Assignees

• Texas Instruments Inc
• Texas Instruments Inc

Inventors

• Shrivastava Neeraj
• Joshi Supreet
• Varshney Himanshu
• Kaviladath Jafar Sadique
• Pentakota Visvesvaraya
• Dusad Shagun

Classifications

• H03M1/1009 Primary

  Calibration · CPC title

• H03M1/785

  using resistors, i.e. R-2R ladders · CPC title

• H03M1/742 Primary

  using current sources as quantisation value generators · CPC title

• H03M1/1019

  by storing a corrected or correction value in a digital look-up table · CPC title

• H03M1/66

  Digital/analogue converters ({H03M1/001 – } H03M1/10 take precedence) · CPC title