Face bonded semiconductor device with through oxide via and metal plug

Patent metadata

Field	Value
Publication number	US-12506050-B1
Application number	US-202418939075-A
Country	US
Kind code	B1
Filing date	Nov 6, 2024
Priority date	Nov 6, 2024
Publication date	Dec 23, 2025
Grant date	Dec 23, 2025

Abstract

A bonded semiconductor device includes a first semiconductor device, a second semiconductor device face bonded to the first semiconductor device, at least one metal plug in a middle of line layer of the first semiconductor device, and a through oxide via (TOV) coupled to the at least one metal plug and a metal line in a backside region of the first semiconductor device.

First claim

The invention claimed is:

1 . A bonded semiconductor device comprising:
a first semiconductor device; a second semiconductor device face bonded to the first semiconductor device; at least one metal plug in a middle of line layer of the first semiconductor device; and a through oxide via (TOV) that physically contacts the at least one metal plug and is coupled to a metal line located in a backside region of the first semiconductor device.

2 . The bonded semiconductor device of claim 1 , wherein sides of the at least one metal plug contact sides of the TOV.

3 . The bonded semiconductor device of claim 1 , wherein the at least one metal plug comprises at least two adjacent bar-shaped metal plugs.

4 . The bonded semiconductor device of claim 3 , wherein the TOV contacts a face and at least one sidewall of each of the two bar-shaped metal plugs.

5 . The bonded semiconductor device of claim 1 , wherein a first end of the at least one metal plug is coupled to the TOV, and a second end of the at least one metal plug is coupled to a metal structure in metal layer M1.

6 . The bonded semiconductor device of claim 1 , wherein the at least one metal plug comprises an array of four or more metal plugs spaced apart from one another.

7 . The bonded semiconductor device of claim 1 , wherein the at least one metal plug comprises a tungsten material.

8 . The bonded semiconductor device of claim 1 , wherein the metal line comprises an aluminum material.

9 . The bonded semiconductor device of claim 1 , wherein the TOV extends through a backside insulation layer and a device layer of the first semiconductor device.

10 . The bonded semiconductor device of claim 1 , wherein the at least one metal plug is a single metal plug and the TOV is recessed into the single metal plug.

11 . The bonded semiconductor device of claim 1 , wherein the at least one metal plug and the TOV are laterally adjacent to a crack stop region and between the crack stop region and active structures of the first semiconductor device.

12 . The bonded semiconductor device of claim 1 , wherein the at least one metal plug spans a width that is greater than a width of the TOV at an interface between the at least one metal plug and the TOV.

13 . The bonded semiconductor device of claim 12 , wherein the width spanned by the at least one metal plug is from 0.5 microns to 1.0 microns, and the width of the TOV is from 0.4 microns to 0.9 microns.

14 . The bonded semiconductor device of claim 1 , wherein the at least one metal plug comprises a plurality of metal plugs.

15 . A three-dimensional integrated circuit (3DIC) comprising:
a first semiconductor device; a second semiconductor device face bonded to the first semiconductor device; at least one metal plug in a middle of line layer of the first semiconductor device; and a through oxide via (TOV) comprising a first end that physically contacts the at least one metal plug and is coupled to a second end coupled to a metal line located in a backside region of the first semiconductor device.

16 . The 3DIC of claim 15 , wherein the at least one metal plug comprises a plurality of metal plugs.

17 . The 3DIC of claim 16 , wherein the at least one metal plug comprises at least two adjacent bar-shaped metal plugs.

18 . The 3DIC of claim 15 , wherein the at least one metal plug comprises an array of four or more metal plugs spaced apart from one another.

19 . The 3DIC of claim 15 , wherein the at least one metal plug spans a width that is greater than a width of the TOV at an interface between the at least one metal plug and the TOV.

20 . A three-dimensional integrated circuit (3DIC) comprising:
a first semiconductor device; a second semiconductor device face bonded to the first semiconductor device; at least one metal plug in a middle of line layer of the first semiconductor device; and a through oxide via (TOV) comprising a first end coupled to the at least one metal plug and a second end coupled to a metal line in a backside region of the first semiconductor device, wherein sides of the at least one metal plug physically contact sides of the TOV.

Assignees

• Globalfoundries Sg Pte Ltd

Inventors

• Wong Qiying
• Yi Wanbing
• Setiawan Yudi
• Nagalinggam Vel Murugan
• Lin Kemao

Classifications

• H10W90/792

  between multiple chips · CPC title

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W90/26

  the stacked chips being of the same size without any chips being laterally offset, e.g. chip stacks having a rectangular shape · CPC title

• H10W80/327

  characterised by the direct bonding of insulating parts, e.g. of silicon oxide layers · CPC title

• H10W80/312

  characterised by the direct bonding of electrically conductive pads · CPC title