Multi-layer semiconductor devices fabricated using a combination of substrate and via structures and fabrication techniques

Patent metadata

Field	Value
Publication number	US-9881904-B2
Application number	US-201515303800-A
Country	US
Kind code	B2
Filing date	Nov 5, 2015
Priority date	Nov 5, 2014
Publication date	Jan 30, 2018
Grant date	Jan 30, 2018

Abstract

A multi-layer semiconductor device includes two or more semiconductor sections, each of the semiconductor sections including at least at least one device layer having first and second opposing surfaces and a plurality of electrical connections extending between the first and second surfaces. The electrical connections correspond to first conductive structures. The multi-layer semiconductor device also includes one or more second conductive structures which are provided as through oxide via (TOV) or through insulator via (TIV) structures. The multi-layer semiconductor device additionally includes one or more silicon layers. At least a first one of the silicon layers includes at least one third conductive structure which is provided as a through silicon via (TSV) structure. The multi-layer semiconductor device further includes one or more via joining layers including at least one fourth conductive structure. A corresponding method for fabricating a multi-layer semiconductor device is also provided.

First claim

The invention claimed is:

1. A multi-layer semiconductor device, comprising:
two or more functional semiconductor sections, each of the functional semiconductor sections having first and second opposing surfaces and consisting of:
at least one insulating layer having a first surface corresponding to the first surface of said functional semiconductor section and having a second opposing surface; and
at least one device layer having a first surface disposed on the second surface of said insulating layer and having a second opposing surface corresponding to the second surface of said functional semiconductor section each of said at least one device layers including at least one circuit device; and
a plurality of first conductive via structures coupled to at least one of said at least one circuit devices so as to form one or more electrical connections extending between the first and second surfaces of said device layer;

one or more second conductive via structures extending through at least a portion of at least one of the two or more functional semiconductor sections, and electrically coupled to select ones of the electrical connections in the at least one of the two or more functional semiconductor sections, the second conductive structures provided as one of: a through oxide via (TOV) structure; or a through insulator via (TIV) structure;
one or more silicon layers having first and second opposing surfaces, wherein at least a first one of the silicon layers includes at least one through silicon via (TSV) structure which extends between the first and second surfaces of the first one of the silicon layers, and is electrically coupled to at least one of the second conductive via structures to form one or more electrical connections between the first one of the silicon layers and one or more of the functional semiconductor sections; and
a via joining layer disposed between and coupled to two of the functional semiconductor sections, said via joining layer including:
at least one fourth conductive via structure extending between first and second surfaces of the via joining layer, wherein the at least one fourth conductive via structure is disposed to form one or more electrical connections between the two functional semiconductor sections.

2. The semiconductor device of claim 1 wherein:
the first conductive via structures are provided as one of: a through oxide via (TOV) structure; or a through insulator via (TIV) structure; and
at least one of the at least one fourth conductive via structure includes at least one of:
a submicron via provided as a via-first TSV; and
a submicron via provided as a via-last TSV.

3. The semiconductor device of claim 1 wherein the at least one fourth conductive via structure is provided as one of: a through oxide via (TOV) structures; or a through insulator via (TIV) structure.

4. The semiconductor device of claim 1 wherein first select ones of the first conductive via structures, first select ones of the second conductive via structures, the at least one third conductive via structure, and the at least one fourth conductive via structure are electrically coupled to form an interconnect structure which extends through each of semiconductor sections, each of the via joining layers and the first one of the silicon layers.

5. The semiconductor device of claim 1 wherein the semiconductor device comprises three functional semiconductor sections, wherein:
the first surface of a first one of the three functional semiconductor sections is disposed over and coupled to the second surface of the first one of the silicon layers;
the first surface of a second one of the semiconductor sections is disposed over and coupled to the second surface of the first one of the semiconductor sections; and
a first one of the via joining layers is disposed between and coupled to the second surface of the second one of the semiconductor sections and the second surface of a third one of the semiconductor sections.

6. The semiconductor device of claim 5 wherein the functional semiconductor sections comprises a second conductive via structure which extends from and forms an electrical connection between first select ones of the electrical connections in the first one of the functional semiconductor sections, first select ones of the electrical connections in the second one of the functional semiconductor sections, and the second surface of the second one of the functional semiconductor sections, wherein the second conductive structure is electrically coupled to the at least one fourth conductive via structure in the first one of the via joining layers.

7. The semiconductor device of claim 5 wherein the first and third ones of the functional semiconductor sections are each fabricated using bulk semiconductor fabrication techniques, and the second one of the functional semiconductor sections is fabricated using at least Silicon-On-Insulator (SOI) fabrication techniques.

8. The semiconductor device of claim 5 wherein the first one of the functional semiconductor sections and the second one of the functional semiconductor sections are each provided as part of a first semiconductor structure, the third one of the semiconductor sections is provided as part of a second semiconductor structure, and the first one of the via joining layers electrically couples the second semiconductor structure to the first semiconductor structure.

9. The semiconductor device of claim 5 wherein the second one of the functional semiconductor sections is electrically coupled to the first one of the functional semiconductor sections using via-last techniques.

10. The semiconductor device of claim 9 wherein the third one of the functional semiconductor sections is electrically coupled to the second one of the functional semiconductor sections using via-first techniques.

11. The semiconductor device of claim 1 wherein the first and second surfaces of the functional semiconductor sections each include or are coated with a bondable dielectric material.

12. The semiconductor device of claim 1 wherein a predetermined distance of between about eight micrometers (μm) and about twelve μm exists between the first and second surfaces of the first one of the silicon layers, wherein the predetermined distance corresponds to a height of the first one of the silicon layers.

13. The semiconductor device of claim 1 wherein a predetermined distance of between about six μm and about eight μm exists between the first and second surfaces of each of the semiconductor sections, wherein the predetermined distance corresponds to a height of the semiconductor sections.

14. The semiconductor device of claim 1 wherein a predetermined distance of between about one μm and about three μm exists between the first and second surface of each of the via joining layers, wherein the predetermined distance corresponds to a height of the via joining layers.

15. The semiconductor device of claim 1 wherein a second one of the silicon layers includes at least one third conductive via structure which extends between select portions of the first and second surfaces of the second one of the silicon layers.

16. The semiconductor device of 16 wherein the semiconductor device comprises four functional semiconductor sections, wherein:
the first surface of a first one of the functional semiconductor sections is disposed over and coupled to the second surface of the first one of the silicon layers;
the first surface of a second one of the functional semiconductor sections is disposed over and coupled to the second surface of the first one of the functional se

Assignees

• Massachusetts Inst Technology

Inventors

• Das Rabindra N
• Gouker Mark A
• Gouker Pascale
• Johnson Leonard M
• Johnson Ryan C

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W90/22

  the stacked chips being on both top and bottom sides of a package substrate, interposer or RDL · CPC title

• H10W90/20

  Configurations of stacked chips · CPC title