Air gap with inverted T-shaped lower portion extending through at least one metal layer, and related method

Patent metadata

Field	Value
Publication number	US-12500119-B2
Application number	US-202217807905-A
Country	US
Kind code	B2
Filing date	Jun 21, 2022
Priority date	Jun 21, 2022
Publication date	Dec 16, 2025
Grant date	Dec 16, 2025

Abstract

Methods of forming semiconductor devices including an air gap extending through at least one metal layer, and the semiconductor device so formed, are disclosed. The air gap has a lower portion that contacts a silicide layer over a gate body of a transistor gate and has an inverted T-shape over the gate body. The air gap reduces the capacitance between a transistor gate in a device layer and adjacent wires and vias used to contact the source and drain of the transistor.

First claim

What is claimed is:

1 . A semiconductor device, comprising:
a device layer including a transistor gate having a silicide layer over a gate body; at least one metal layer over the device layer, the at least one metal layer including a dielectric with a conductor therein; and an air gap extending through the dielectric of the at least one metal layer, wherein a lower portion of the air gap within the dielectric contacts the silicide layer over the gate body, and the air gap includes a lowermost surface below the silicide layer interfacing with an upper surface of an etch stop layer adjacent the gate body, and has an inverted T-shape over the gate body.

2 . The semiconductor device of claim 1 , wherein the at least one metal layer includes at least a first metal layer over the device layer and a second metal layer over the first metal layer.

3 . The semiconductor device of claim 1 , further comprising at least one cap layer over each metal layer, wherein the air gap surrounds an edge of the at least one cap layer over each metal layer.

4 . The semiconductor device of claim 1 , wherein the at least one metal layer includes a first metal layer that is part of a first interconnect layer also including a first via layer, and a second metal layer that is part of a second interconnect layer also including a second via layer, wherein the air gap extends through the second via layer and part of the first via layer.

5 . The semiconductor device of claim 1 , further comprising a dielectric layer sealing the air gap, and lining a sidewall of the dielectric of the at least one metal layer.

6 . The semiconductor device of claim 1 , wherein the air gap extends below an upper surface of the silicide layer.

7 . The semiconductor device of claim 6 , wherein the air gap extends adjacent an upper portion of the gate body.

8 . A radio frequency semiconductor-on-insulator (RFSOI) switch, comprising:
a transistor gate in a semiconductor-on-insulator (SOI) device layer of an SOI substrate, the transistor gate includes a silicide layer over a gate body; at least one metal layer over the SOI device layer, the at least one metal layer including a dielectric with a conductor therein; and an air gap within the dielectric extending through the dielectric of the at least one metal layer, wherein a lower portion of the air gap contacts the silicide layer over the gate body, and the air gap includes a lowermost surface below the silicide layer interfacing with an upper surface of an etch stop layer adjacent the gate body, and has an inverted T-shape over the gate body.

9 . The RFSOI switch of claim 8 , wherein the at least one metal layer includes at least a first metal layer over the device layer and a second metal layer over the first metal layer.

10 . The RFSOI switch of claim 8 , further comprising at least one cap layer over each metal layer, wherein the air gap is adjacent to an edge of the at least one cap layer over each metal layer.

11 . The RFSOI switch of claim 8 , wherein the at least one metal layer includes a first metal layer that is part of a first interconnect layer also including a first via layer, and a second metal layer that is part of a second interconnect layer also including a second via layer, wherein the air gap extends through the second via layer and part of the first via layer.

12 . The RFSOI switch of claim 8 , further comprising a dielectric layer sealing the air gap, and lining a sidewall of the dielectric of the at least one metal layer.

13 . The RFSOI switch of claim 8 , wherein the air gap extends below an upper surface of the silicide layer.

14 . The RFSOI switch of claim 13 , wherein the air gap extends adjacent an upper portion of the gate body.

15 . A method, comprising:
forming an opening through a dielectric of at least one metal layer over a transistor gate, the opening exposing an etch stop layer (ESL) over a silicide layer over a gate body of the transistor enlarging the opening over the transistor gate to remove the ESL and expose the silicide layer over the transistor gate, the enlarging of the opening undercutting the dielectric over the transistor gate; and forming an air gap by forming a dielectric layer over the opening to seal the opening, wherein a lower portion of the air gap within the dielectric contacts the silicide layer over the gate body and the air gap includes a lower surface below the silicide layer interfacing with an upper surface of the etch stop layer adjacent the gate body, and has an inverted T-shape over the gate body.

16 . The method of claim 15 , wherein the forming the opening includes performing a reactive ion etch (RIE), and the enlarging includes treating the etch stop layer and exposing the opening to a diluted hydrofluoric (DHF) acid etch.

17 . The method of claim 15 , wherein the enlarging extends the opening to below an upper surface of the silicide layer and to extend along an upper portion of the gate body, and wherein the air gap extends below the upper surface of the silicide layer.

18 . The method of claim 15 , wherein the enlarging extends the opening to surround an edge of at least one cap layer over the at least one metal layer, and wherein the air gap adjacent to the edge of the at least one cap layer over the at least one metal layer.

19 . The method of claim 15 , wherein the at least one metal layer includes a first metal layer that is part of a first interconnect layer also including a first via layer, and a second metal layer that is part of a second interconnect layer also including a second via layer, wherein the air gap extends through the second via layer and part of the first via layer.

20 . The method of claim 15 , wherein the forming the air gap lines a sidewall of the dielectric of the at least one metal layer with the dielectric layer.

Assignees

• Globalfoundries Sg Pte Ltd

Inventors

• Deng Wensheng
• Lin Kemao
• Hsieh Curtis Chun-I
• Yi Wanbing
• Xinfu Liu
• Toh Rui Tze
• Shao Yanxia
• Yin Shucheng
• Wong Jason Kin Wei
• Chong Yung Fu

Classifications

• H10W20/074

  of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers · CPC title

• H10W20/47

  comprising two or more dielectric layers having different properties, e.g. different dielectric constants · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H10W20/072 Primary

  of dielectric parts comprising air gaps · CPC title

• H10W20/495

  Capacitive arrangements or effects of, or between wiring layers · CPC title