Air gap over transistor gate and related method

Patent metadata

Field	Value
Publication number	US-10157777-B2
Application number	US-201615152797-A
Country	US
Kind code	B2
Filing date	May 12, 2016
Priority date	May 12, 2016
Publication date	Dec 18, 2018
Grant date	Dec 18, 2018

Abstract

A semiconductor device may include a transistor gate in a device layer; an interconnect layer over the device layer; and an air gap extending through the interconnect layer to contact an upper surface of the transistor gate. The air gap provides a mechanism to reduce both on-resistance and off-capacitance for applications using SOI substrates such as radio frequency switches.

First claim

What is claimed is:

1. A method of forming an air gap for a semiconductor device, the method comprising:
forming an air gap mask exposing a portion of an interconnect layer over a device layer, the device layer including a transistor gate therein;
etching an opening through the interconnect layer using the air gap mask above the transistor gate, the opening exposing sidewalls of a dielectric of the interconnect layer;
removing the air gap mask;
after removing the air gap mask, recessing the exposed sidewalls of the dielectric of the interconnect layer in the opening; and
forming an air gap over the transistor gate by depositing an air gap capping layer to seal the opening at a surface of the interconnect layer.

2. The method of claim 1 , wherein the interconnect layer includes a local interconnect layer over the device layer and a first metal layer over the local interconnect layer, and the dielectric of the interconnect layer about the air gap covers any conductive wire in the first metal layer or any conductive via in the local interconnect layer.

3. The method of claim 1 , wherein the local interconnect layer includes a local interconnect cap layer at an upper surface thereof, and the first metal layer includes a first metal cap layer at an upper surface thereof, and wherein recessing the exposed sidewalls of the dielectric of the interconnect layer in the opening exposes an edge of at least one of the local interconnect cap layer and the first metal cap layer in the opening.

4. The method of claim 3 , wherein forming the air gap over the transistor gate by depositing the air gap capping layer to seal the opening at the surface of the interconnect layer includes the edge of the first metal cap layer in the opening pinching off the air gap capping layer to form the air gap.

5. The method of claim 2 , wherein the first metal layer includes a metal wire extending laterally parallel to the transistor gate in the device layer, and wherein the air gap vertically extends above and below the metal wire.

6. The method of claim 1 , wherein the air gap vertically extends only partially into the air gap capping layer.

7. The method of claim 1 , wherein the transistor gate includes a body, a silicide layer over the body and an etch stop layer over the silicide layer.

8. The method of claim 7 , wherein one of recessing the exposed sidewalls of the dielectric of the interconnect layer in the opening after removing the air gap mask and etching the opening removes at least a portion of the etch stop layer over the silicide layer, and wherein the air gap contacts the etch stop layer.

9. The method of claim 7 , wherein one of recessing the exposed sidewalls of the dielectric of the interconnect layer in the opening after removing the air gap mask and etching the opening removes the etch stop layer over the silicide layer, and wherein the air gap contacts the silicide layer.

10. The method of claim 7 , wherein one of recessing the exposed sidewalls of the dielectric of the interconnect layer in the opening after removing the air gap mask and etching the opening removes the etch stop layer over the silicide layer and removes the silicide layer over the body, and wherein the air gap contacts the body of the transistor gate.

11. The method of claim 1 , wherein forming the air gap over the transistor gate by depositing the air gap capping layer to seal the opening at the surface of the interconnect layer includes chemical vapor depositing (CVD) a dielectric.

12. The method of claim 1 , wherein etching the opening through the interconnect layer using the air gap mask includes etching a laterally elongate opening above the transistor gate, and wherein forming the air gap over the transistor gate by depositing the air gap capping layer includes sealing the laterally elongate opening.

13. The method of claim 1 , wherein etching the opening through the interconnect layer using the air gap mask includes etching a portion of the opening in a laterally disposed T-shape, and wherein forming the air gap over the transistor gate by depositing the air gap capping layer includes sealing the portion of the opening in the laterally disposed T-shape.

14. The method of claim 1 , wherein etching the opening through the interconnect layer using the air gap mask includes etching the opening such that the opening has a first width laterally adjacent a contact and a second width wider than the first width laterally between contacts.

15. A method of forming an air gap for a semiconductor device, the method comprising:
forming an air gap mask exposing a portion of an interconnect layer over a device layer, the interconnect layer including a local interconnect layer over the device layer and a first metal layer over the local interconnect layer and the local interconnect layer includes a local interconnect cap layer at an upper surface thereof and the first metal layer includes a first metal cap layer at an upper surface thereof, and wherein the device layer includes a transistor gate having a body, a silicide layer over the body and an etch stop layer over the silicide layer;
etching an opening through the interconnect layer using the air gap mask above the transistor gate, the opening exposing sidewalls of a dielectric of the interconnect layer;
removing the air gap mask;
recessing the exposed sidewalls of the dielectric of the interconnect layer in the opening, the recessing exposing an edge of at least one of the local interconnect cap layer and the first metal cap layer in the opening; and
forming an air gap over the transistor gate by depositing an air gap capping layer to seal the opening at a surface of the interconnect layer, wherein the dielectric of the interconnect layer about the air gap covers any conductive wire in the first metal layer or any conductive via in the local interconnect layer.

16. The method of claim 15 , wherein the first metal layer includes a metal wire extending laterally parallel to the transistor gate in the device layer, and wherein the air gap vertically extends above and below the metal wire.

17. The method of claim 15 , wherein one of recessing the exposed sidewalls of the dielectric of the interconnect layer in the opening and etching the opening removes at least a portion of the etch stop layer over the silicide layer, and wherein the air gap contacts the etch stop layer.

18. The method of claim 15 , wherein one of recessing the exposed sidewalls of the dielectric of the interconnect layer in the opening and etching the opening removes the etch stop layer over the silicide layer, and wherein the air gap contacts the silicide layer.

19. The method of claim 13 , wherein etching the opening through the interconnect layer using the air gap mask includes etching the opening such that the opening has a first width laterally adjacent a contact and a second width wider than the first width laterally between contacts.

Assignees

• Globalfoundries Inc

Inventors

• He Zhong-Xiang
• Jaffe Mark D
• Wolf Randy L
• Joseph Alvin J
• Cucci Brett T
• Stamper Anthony K

Classifications

• H10P50/73

  using masks for insulating materials · CPC title

• H10P50/71

  using masks for conductive or resistive materials · CPC title

• H10P14/6334

  using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition (deposition by physical ablation of a target H10P14/6329) · CPC title

• H10W20/40

  Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes · CPC title

• H10W44/20

  at high-frequency [HF] or radio frequency [RF] · CPC title