Field-effect transistor, method of manufacturing the same, and radio-frequency device

Patent metadata

Field	Value
Publication number	US-9659865-B2
Application number	US-201514897867-A
Country	US
Kind code	B2
Filing date	Mar 25, 2015
Priority date	Apr 18, 2014
Publication date	May 23, 2017
Grant date	May 23, 2017

Abstract

There is provided a field-effect transistor including: a gate electrode; a semiconductor layer having a source region and a drain region with the gate electrode in between; contact plugs provided on the source region and the drain region; first metals stacked on the contact plugs; and a low-dielectric constant region provided in a region between the first metals along an in-plane direction of the semiconductor layer and provided at least in a first region below bottom surfaces of the first metals along a stacking direction.

First claim

The invention claimed is:

1. A field-effect transistor comprising:
a gate electrode;
a semiconductor layer having a source region and a drain region with the gate electrode in between;
contact plugs comprising a first conductive material, wherein a first contact plug of the contact plugs is provided on the source region, and wherein a second contact plug of the contact plugs is provided on the drain region;
first metals comprising a second conductive material that is different than the first conductive material, wherein one of the first metals is stacked on the first contact plug, and wherein a second one of the first metals is stacked on the second contact plug; and
a low-dielectric constant region provided in a region between the first metals along an in-plane direction of the semiconductor layer and provided at least in a first region below bottom surfaces of the first metals along a stacking direction.

2. The field-effect transistor according to claim 1 , wherein the low-dielectric constant region is provided in the first region and a second region between the bottom surfaces of the first metals and top surfaces of the first metals, along the stacking direction.

3. The field-effect transistor according to claim 2 , wherein the low-dielectric constant region is provided in the first region, the second region, and a third region above the top surfaces of the first metals, along the stacking direction.

4. The field-effect transistor according to claim 3 , further comprising:
one or more insulating films provided on the semiconductor layer; and
an opening opened from a top surface of the one or more insulating films toward a top surface of the gate electrode,
wherein the low-dielectric constant region is provided in the opening.

5. The field-effect transistor according to claim 4 , wherein the one or more insulating films include a plurality of insulating films with different etching rates.

6. The field-effect transistor according to claim 4 , wherein
the one or more insulating films include
a first insulating film covering a surface of the gate electrode and a top surface of the semiconductor layer,
a second insulating film covering a surface of the first insulating film, and
a third insulating film provided between a surface of the second insulating film and the bottom surfaces of the first metals, and
the second insulating film is made of a material with a different etching rate from etching rates of the first insulating film and the third insulating film, and
the opening is opened to a top surface of the second insulating film through at least the third insulating film.

7. The field-effect transistor according to claim 6 , wherein the low-dielectric constant region is provided with a width equal to or smaller than a width of a region where the surface of the gate electrode is covered with the first insulating film and the second insulating film.

8. The field-effect transistor according to claim 6 , wherein the low-dielectric constant region is provided with a larger width than a width of a region where the surface of the gate electrode is covered with the first insulating film and the second insulating film.

9. The field-effect transistor according to claim 6 , wherein
the one or more insulating films further include a fourth insulating film covering a top surface of the third insulating film and surfaces of the first metals, and
the opening is opened from a top surface of the fourth insulating film to the top surface of the second insulating film.

10. The field-effect transistor according to claim 9 , wherein the low-dielectric constant region comprises a fifth insulating film that fills at least a part of the opening, the fifth insulating film being made of a material with a lower dielectric constant than dielectric constants of the third insulating film and the fourth insulating film.

11. The field-effect transistor according to claim 9 , wherein
the one or more insulating films further include a fifth insulating film on the fourth insulating film,
the low-dielectric constant region comprises an air gap provided at least in a part of the opening, and
a top of the air gap is blocked by the fifth insulating film.

12. The field-effect transistor according to claim 11 , wherein a side surface and a bottom surface of the opening are covered with the fifth insulating film.

13. The field-effect transistor according to claim 11 , further comprising a second metal between the fourth insulating film and the fifth insulating film,
wherein the one or more insulating films further include a seventh insulating film covering the top surface of the fourth insulating film and a surface of the second metal, and
the opening is opened from a top surface of the seventh insulating film to the top surface of the second insulating film.

14. The field-effect transistor according to claim 1 , wherein
the gate electrode extends along one direction, and
the contact plugs, the first metals, and the low-dielectric constant region extend in parallel with the gate electrode.

15. The field-effect transistor according to claim 1 , further comprising:
a device region in which the source region and the drain region are provided in the semiconductor layer;
a wiring region including a multilayer wiring section; and
a device isolation layer that partitions the device region and the wiring region,
wherein the low-dielectric constant region is provided in the device region.

16. The field-effect transistor according to claim 15 , further comprising:
an active region including the device region and the wiring region; and
a device isolation region provided outside the active region, and including the device isolation layer,
wherein the device isolation region includes a gate contact coupled to the gate electrode and provided on the device isolation layer, and
the low-dielectric constant region is provided while avoiding the gate contact.

17. The field-effect transistor according to claim 1 , wherein
the gate electrode extends along one direction,
the contact plugs and the first metals extend in parallel with the gate electrode, and
the low-dielectric constant region extends along a direction intersecting with the gate electrode.

18. The field-effect transistor according to claim 1 , wherein
the gate electrode includes a plurality of finger sections extending along a same direction, and a coupling section that couples the plurality of finger sections to one another, and
the low-dielectric constant region is provided above the plurality of finger sections or above at least a part of the coupling section.

19. The field-effect transistor according to claim 1 , wherein the low-dielectric constant region provided in the region between the first metals along the in-plane direction of the semiconductor layer and provided at least in the first region below the bottom surfaces of the first metals along the stacking direction is a single low-dielectric constant region.

20. The field-effect transistor according to claim 19 , wherein the single low-dielectric constant region is a single air gap.

21. A radio frequency device provided with a field-effect transistor, the field-effect transistor comprising:
a gate electrode;
a semiconductor layer having a source region and a drain region with the gate electrode in between;
contact plugs comprising a first conductive material, wherein a first contact plug of the contact plugs is provided on the source region, and wherein a second contact plu

Assignees

• Sony Corp

Inventors

• Saka Naoki
• Okamoto Daisaku
• Tanaka Hideki

Classifications

• H10W20/495

  Capacitive arrangements or effects of, or between wiring layers · CPC title

• H10W20/484 Primary

  Interconnections having extended contours, e.g. pads having mesh shape or interconnections comprising connected parallel stripes · CPC title

• H10W20/47

  comprising two or more dielectric layers having different properties, e.g. different dielectric constants · CPC title

• H10W20/43

  Layouts of interconnections · CPC title

• H10W20/40

  Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes · CPC title