Multithread framework for use in pre-boot environment of a system-on-chip

US2019332425A1 · US · A1

Patent metadata
FieldValue
Publication numberUS-2019332425-A1
Application numberUS-201816203386-A
CountryUS
Kind codeA1
Filing dateNov 28, 2018
Priority dateApr 30, 2018
Publication dateOct 31, 2019
Grant date

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

Various aspects are described herein. In some aspects, the disclosure provides a method for a system-on-chip (SoC) including one or more computing cores. The method includes providing a scheduler to schedule running of threads on the one or more computing cores in a pre-boot environment including a core thread configured to provide a plurality of services. The method further includes providing, by the scheduler, a first lock for the core thread. The method further includes initializing, by the core thread, one or more additional services separate from the plurality of services. The method further includes selectively allowing access to the plurality of services of the core thread to one or more additional threads based on a status of the first lock. The method further includes allowing access to the one or more additional services to the one or more additional threads independent of the status of the first lock.

First claim

Opening claim text (preview).

What is claimed is: 1 . A method of enabling a multithread framework in a pre-boot environment for a system-on-chip (SoC) comprising one or more computing cores, the method comprising: providing a scheduler to schedule running of a plurality of threads on the one or more computing cores in the pre-boot environment, the plurality of threads comprising a core thread configured to provide a plurality of services and one or more additional threads; providing, by the scheduler, a first lock for the core thread; initializing, by the core thread, one or more additional services separate from the plurality of services; selectively allowing access to the plurality of services of the core thread to the one or more additional threads based on a status of the first lock; and allowing access to the one or more additional services to the one or more additional threads independent of the status of the first lock. 2 . The method of claim 1 , further comprising providing, by the scheduler, one or more additional locks for the one or more additional services, wherein allowing access to the one or more additional services to the one or more additional threads comprises selectively allowing access to the one or more additional services to the one or more additional threads based on status of the one or more additional locks. 3 . The method of claim 1 , further comprising: acquiring, by a first thread of the one or more additional threads, the first lock when calling one of the plurality of services; and releasing the first lock when returning from the one of the plurality of services. 4 . The method of claim 1 , further comprising: launching the scheduler prior to executing the core thread; and launching the core thread by the scheduler. 5 . The method of claim 1 , wherein one of the plurality of threads comprises a timer thread configured to provide interrupt service to the core thread. 6 . The method of claim 5 , further comprising: upon receiving an interrupt event, determining by the timer thread if the core thread is running an idle process; indicating by the timer thread to the idle process to return from idle when the core thread is running the idle process; and issuing a timer callback to the core thread when the core thread is not running the idle process. 7 . The method of claim 1 , further comprising: acquiring, by a first thread of the one or more additional threads, the first lock when making a raise task priority list call; and releasing the first lock when making a restore task priority list call. 8 . The method of claim 1 , wherein the pre-boot environment comprises a Unified Extensible Firmware Interface (UEFI) pre-boot environment. 9 . A system-on-chip (SoC) comprising: a memory; and one or more computing cores coupled to the memory, the one or more computing cores being configured to: provide a scheduler to schedule running of a plurality of threads on the one or more computing cores in a pre-boot environment, the plurality of threads comprising a core thread configured to provide a plurality of services and one or more additional threads; provide, by the scheduler, a first lock for the core thread; initialize, by the core thread, one or more additional services separate from the plurality of services; selectively allow access to the plurality of services of the core thread to the one or more additional threads based on a status of the first lock; and allow access to the one or more additional services to the one or more additional threads independent of the status of the first lock. 10 . The SoC of claim 9 , wherein the one or more computing cores are further configured to provide, by the scheduler, one or more additional locks for the one or more additional services, wherein allowing access to the one or more additional services to the one or more additional threads comprises selectively allowing access to the one or more additional services to the one or more additional threads based on status of the one or more additional locks. 11 . The SoC of claim 9 , wherein the one or more computing cores are further configured to: acquire, by a first thread of the one or more additional threads, the first lock when calling one of the plurality of services; and release the first lock when returning from the one of the plurality of services. 12 . The SoC of claim 9 , wherein the one or more computing cores are further configured to: launch the scheduler prior to executing the core thread; and launch the core thread by the scheduler. 13 . The SoC of claim 9 , wherein one of the plurality of threads comprises a timer thread configured to provide interrupt service to the core thread. 14 . The SoC of claim 13 , wherein the one or more computing cores are further configured to: upon receiving an interrupt event, determine by the timer thread if the core thread is running an idle process; indicate by the timer thread to the idle process to return from idle when the core thread is running the idle process; and issue a timer callback to the core thread when the core thread is not running the idle process. 15 . The SoC of claim 9 , wherein the one or more computing cores are further configured to: acquire, by a first thread of the one or more additional threads, the first lock when making a raise task priority list call; and release the first lock when making a restore task priority list call. 16 . The SoC of claim 9 , wherein the pre-boot environment comprises a Unified Extensible Firmware Interface (UEFI) pre-boot environment. 17 . A non-transitory computer readable storage medium that stores instructions that when executed by a system-on-chip (SoC) comprising one or more computing cores cause the SoC to perform a method of enabling a multithread framework in a pre-boot environment, the method comprising: providing a scheduler to schedule running of a plurality of threads on the one or more computing cores in the pre-boot environment, the plurality of threads comprising a core thread configured to provide a plurality of services and one or more additional threads; providing, by the scheduler, a first lock for the core thread; initializing, by the core thread, one or more additional services separate from the plurality of services; selectively allowing access to the plurality of services of the core thread to the one or more additional threads based on a status of the first lock; and allowing access to the one or more additional services to the one or more additional threads independent of the status of the first lock. 18 . The non-transitory computer readable storage medium of claim 17 , wherein the method further comprises providing, by the scheduler, one or more additional locks for the one or more additional services, wherein allowing access to the one or more additional services to the one or more additional threads comprises selectively allowing access to the one or more additional services to the one or more additional threads based on status of the one or more additional locks. 19 . The non-transitory computer readable storage medium of claim 17 , wherein the method further comprises: acquiring, by a first thread of the one or more additional threads, the first lock when calling one of the plurality of services; and releasing the first lock when returning from the one of the plurality of services. 20 . The non-transitory computer readable storage medium of claim 17 , wherein the method further comprises: launching the scheduler p

Assignees

Inventors

Classifications

  • Precedence · CPC title

  • G06F9/4881Primary

    Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues · CPC title

  • Deadlock detection or avoidance · CPC title

  • Initialisation of multiprocessor systems · CPC title

  • G06F9/526Primary

    Mutual exclusion algorithms · CPC title

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Frequently asked questions

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What does patent US2019332425A1 cover?
Various aspects are described herein. In some aspects, the disclosure provides a method for a system-on-chip (SoC) including one or more computing cores. The method includes providing a scheduler to schedule running of threads on the one or more computing cores in a pre-boot environment including a core thread configured to provide a plurality of services. The method further includes providing,…
Who is the assignee on this patent?
Qualcomm Inc
What technology area does this patent fall under?
Primary CPC classification G06F9/4881. Mapped technology areas include Physics.
When was this patent published?
Publication date Thu Oct 31 2019 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).