Faciltating multi-level microcontroller scheduling for efficient computing microarchitecture

Patent metadata

Field	Value
Publication number	US-2018307533-A1
Application number	US-201715493698-A
Country	US
Kind code	A1
Filing date	Apr 21, 2017
Priority date	Apr 21, 2017
Publication date	Oct 25, 2018
Grant date	—

Abstract

A mechanism is described for facilitating multi-level scheduling of workloads in computing devices. A method of embodiments, as described herein, includes facilitating multiple levels of scheduling for processing of workloads using multiple levels of queues, where the workloads are associated with a device including a processor of a computing device.

First claim

What is claimed is:

1 . An apparatus comprising:
a microcontroller hosting a scheduling mechanism having multi-level processing logic; and the multi-level processing logic, as facilitated by or at least partially incorporated into a processor, to facilitate multiple levels of scheduling for processing of workloads using multiple levels of queues, wherein the workloads are associated with a device including the processor.

2 . The apparatus of claim 1 , wherein the multiple levels of scheduling comprise a first level of scheduling of a first set of the workloads and a second level of scheduling of a second set of the workloads, wherein the first set of the workloads is scheduled to be processed and distributed through a virtual function offering an interface to a virtual machine.

3 . The apparatus of claim 2 , wherein the second level of scheduling of the second set of the workloads to be processed and distributed through multiple virtual functions offering interfaces to multiple virtual machines, wherein the multiple virtual functions include the virtual function, and wherein the multiple virtual machines include the virtual machine.

4 . The apparatus of claim 1 , wherein first level of scheduling is performed through a first level of queue of the multiple levels of queues, and wherein the second level of scheduling is performed through a second level of queue of the multiple levels of queues.

5 . The apparatus of claim 1 , further comprising context and control logic, as facilitated by or at least partially incorporated into the processor, to determine one or more contexts associated with each workload and associate one or more of priorities, weights, and caps to perform one or more of preemption of workloads based on at least one of on-the-fly contexts and round-robin scheduling of the one or more contexts in one or more of the first and second level queues.

6 . The apparatus of claim 5 , wherein the one or more of preemption of workloads are further performed based on at least one of scheduling of the one or more contexts based on one or more of the priorities of queued contexts, proportional scheduling based on one or more of the weights of the queued contexts, and capping a maximum portion of each of the queued contexts.

7 . The apparatus of claim 1 , wherein the processor comprises a graphics processor, wherein the graphics processor is co-located with an application processor on a common semiconductor package.

8 . A method comprising:
facilitating multiple levels of scheduling for processing of workloads using multiple levels of queues, wherein the workloads are associated with a device including a processor of a computing device.

9 . The method of claim 8 , wherein the multiple levels of scheduling comprise a first level of scheduling of a first set of the workloads and a second level of scheduling of a second set of the workloads, wherein the first set of the workloads is scheduled to be processed and distributed through a virtual function offering an interface to a virtual machine.

10 . The method of claim 9 , wherein the second level of scheduling of the second set of the workloads to be processed and distributed through multiple virtual functions offering interfaces to multiple virtual machines, wherein the multiple virtual functions include the virtual function, and wherein the multiple virtual machines include the virtual machine.

11 . The method of claim 8 , wherein first level of scheduling is performed through a first level of queue of the multiple levels of queues, and wherein the second level of scheduling is performed through a second level of queue of the multiple levels of queues.

12 . The method of claim 8 , further comprising determining one or more contexts associated with each workload and associate one or more of priorities, weights, and caps to perform one or more of preemption of workloads based on at least one of on-the-fly contexts and round-robin scheduling of the one or more contexts in one or more of the first and second level queues.

13 . The method of claim 12 , wherein the one or more of preemption of workloads are further performed based on at least one of scheduling of the one or more contexts based on one or more of the priorities of queued contexts, proportional scheduling based on one or more of the weights of the queued contexts, and capping a maximum portion of each of the queued contexts.

14 . The method of claim 8 , wherein the processor comprises a graphics processor, wherein the graphics processor is co-located with an application processor on a common semiconductor package.

15 . At least one machine-readable medium comprising instructions that when executed by a computing device, cause the computing device to perform operations comprising:
facilitating multiple levels of scheduling for processing of workloads using multiple levels of queues, wherein the workloads are associated with a device including a processor of the computing device.

16 . The machine-readable medium of claim 15 , wherein the multiple levels of scheduling comprise a first level of scheduling of a first set of the workloads and a second level of scheduling of a second set of the workloads, wherein the first set of the workloads is scheduled to be processed and distributed through a virtual function offering an interface to a virtual machine.

17 . The machine-readable medium of claim 16 , wherein the second level of scheduling of the second set of the workloads to be processed and distributed through multiple virtual functions offering interfaces to multiple virtual machines, wherein the multiple virtual functions include the virtual function, and wherein the multiple virtual machines include the virtual machine.

18 . The machine-readable medium of claim 15 , wherein first level of scheduling is performed through a first level of queue of the multiple levels of queues, and wherein the second level of scheduling is performed through a second level of queue of the multiple levels of queues.

19 . The machine-readable medium of claim 15 , wherein the operations further comprise determining one or more contexts associated with each workload and associate one or more of priorities, weights, and caps to perform one or more of preemption of workloads based on at least one of on-the-fly contexts and round-robin scheduling of the one or more contexts in one or more of the first and second level queues.

20 . The machine-readable medium of claim 19 , wherein the one or more of preemption of workloads are further performed based on at least one of scheduling of the one or more contexts based on one or more of the priorities of queued contexts, proportional scheduling based on one or more of the weights of the queued contexts, and capping a maximum portion of each of the queued contexts, wherein the processor comprises a graphics processor, wherein the graphics processor is co-located with an application processor on a common semiconductor package.

Assignees

• Intel Corp

Inventors

• Tian Kun
• Cowperthwaite David J
• Ramadoss Murali
• Vembu Balaji
• Wang Zhi
• Samson Eric C
• Koker Altug
• Appu Abhishek R
• Ray Joydeep

Classifications

• G06F9/4881

  Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues · CPC title

• G06F9/5027

  the resource being a machine, e.g. CPUs, Servers, Terminals · CPC title

• G06F9/4831

  with variable priority · CPC title

• G06F9/4887 Primary

  involving deadlines, e.g. rate based, periodic · CPC title

• G06T1/20 Primary

  Processor architectures; Processor configuration, e.g. pipelining · CPC title