User-level interrupts in virtual machines

Patent metadata

Field	Value
Publication number	US-12498963-B2
Application number	US-202117519384-A
Country	US
Kind code	B2
Filing date	Nov 4, 2021
Priority date	Nov 4, 2021
Publication date	Dec 16, 2025
Grant date	Dec 16, 2025

Abstract

A system comprises a physical processor to execute a virtual machine manager to run, on a logical core, a virtual machine including a guest user application and a virtual CPU. Circuitry coupled to an external device is to receive an interrupt request from the external device for the guest user application, locate a first interrupt data structure associated with the guest user application, generate a first interrupt with the first interrupt data structure based on a first interrupt vector for the interrupt request, locate a second interrupt data structure associated with the virtual CPU, and generate a first notification interrupt for the virtual CPU with the second interrupt data structure based on a first notification vector in the first interrupt data structure. The circuitry may generate a second notification interrupt for the logical core using a second notification vector and a logical core identifier from the second interrupt data structure.

First claim

The invention claimed is:

1 . A system comprising:
a physical processor including a logical core, the physical processor to execute a virtual machine manager to run a virtual machine on the logical core, the virtual machine including a guest user application and a virtual central processing unit (CPU); memory to store a first interrupt data structure associated with the guest user application and a second interrupt data structure associated with the virtual CPU; and circuitry communicatively coupled to an external device, the circuitry to:
identify, in a first table, an entry corresponding to an interrupt request received from the external device for the guest user application, wherein the entry includes a first interrupt vector for the guest user application;
obtain, from the entry, the first interrupt vector, a first pointer to the first interrupt data structure, and a second pointer to a second table that associates the first identifier of the virtual CPU to the second interrupt data structure;
locate, based on first information in the entry, the first interrupt data structure including a first notification vector for the virtual CPU and a first identifier of the virtual CPU;
generate a first interrupt for the guest user application with the first interrupt data structure based on the first interrupt vector;
locate the second interrupt data structure based at least in part on second information in the entry and the first identifier of the virtual CPU; and
generate a first notification interrupt for the virtual CPU with the second interrupt data structure based on the first notification vector for the virtual CPU.

2 . The system of claim 1 , wherein the circuitry is further to:
generate a second notification interrupt for the logical core of the physical processor using a second notification vector and a second identifier of the logical core.

3 . The system of claim 2 , wherein the circuitry is further to:
obtain the second notification vector and the second identifier of the logical core from the second interrupt data structure.

4 . The system of claim 1 , wherein the circuitry is further to:
obtain the first identifier of the virtual CPU from the first interrupt data structure; locate a second table that associates a plurality of virtual CPU identifiers to a plurality of second interrupt data structures, respectively; and access the second table using the first identifier to locate the second interrupt data structure of the plurality of second interrupt data structures.

5 . The system of claim 1 , wherein the circuitry is further to:
determine whether a posted type associated with the interrupt request is a user-level posted type, a kernel posted type, or a nested posted type.

6 . The system of claim 1 , wherein the circuitry is further to:
subsequent to receiving the interrupt request, receive a second interrupt request for the guest user application; locate the first interrupt data structure associated with the guest user application; and in response to determining that a previous notification interrupt for the virtual CPU is pending, prevent generating another notification interrupt for the virtual CPU.

7 . The system of claim 1 , wherein the circuitry is further to:
in response to determining that a previous notification interrupt for the logical core of the physical processor is pending, prevent generation of a second notification interrupt for the logical core of the physical processor.

8 . The system of claim 1 , wherein the external device is one of an input/output device or an accelerator.

9 . The system of claim 1 , wherein the physical processor and the circuitry are part of a hardware platform, and wherein the external device is either integrated with the hardware platform or separate from the hardware platform.

10 . An apparatus comprising:
interrupt remapping hardware including circuitry communicatively coupled to an external device and a physical processor including a logical core, the circuitry to:
receive an interrupt request from the external device for a guest user application running on a virtual central processing unit (CPU) in a virtual machine instantiated by a virtual machine manager (VMM) executed by the physical processor;
identify, in a first table, an entry corresponding to the interrupt request and including a first interrupt vector for the guest user application;
obtain, from the entry, the first interrupt vector, a first pointer to a first interrupt data structure, and a second pointer to a second table that associates the first identifier of the virtual CPU to the second interrupt data structure;
use first information in the entry to locate the first interrupt data structure in memory, wherein the first interrupt data structure includes a first notification vector for the virtual CPU and a first identifier of the virtual CPU;
generate a first interrupt for the guest user application by setting a first portion of the first interrupt data structure based on the first interrupt vector;
use second information in the entry and the first identifier of the virtual CPU to locate a second interrupt data structure in the memory; and
generate a first notification interrupt for the virtual CPU by setting a second portion of the second interrupt data structure based on the first notification vector for the virtual CPU.

11 . The apparatus of claim 10 , wherein the circuitry is further to:
generate a second notification interrupt for the logical core of the physical processor using a second notification vector and a second identifier of the logical core.

12 . The apparatus of claim 11 , wherein the circuitry is further to:
obtain the second notification vector and the second identifier of the logical core from the second interrupt data structure.

13 . The apparatus of claim 10 , wherein the circuitry is further to:
obtain the first identifier of the virtual CPU from the first interrupt data structure; locate a second table that associates a plurality of virtual CPU identifiers to a plurality of second interrupt data structures, respectively; and access the second table using the first identifier to locate the second interrupt data structure of the plurality of second interrupt data structures.

14 . The apparatus of claim 10 , wherein the circuitry is further to:
determine whether a posted type associated with the interrupt request is a user-level posted type, a kernel posted type, or a nested posted type.

15 . The apparatus of claim 10 , wherein the circuitry is further to:
in response to determining that notification interrupts are to be suppressed for the logical core of the physical processor, prevent generation of a second notification interrupt for the logical core of the physical processor.

16 . A method comprising:
receiving, by circuitry in a hardware platform, an interrupt request from an external device communicatively coupled to the circuitry, wherein the interrupt request targets a guest user application running on a virtual central processing unit (CPU) in a virtual machine corresponding to a logical core of a physical processor in the hardware platform; identifying, in a first table, an entry corresponding to the interrupt request and including a first interrupt vector for the guest user application; obtaining, from the entry, the first interrupt vector, a first pointer to a first interrupt data structure, and a second pointer to a second table that associates the first identifier of the virtual CPU to the second interrupt data structure; using a first pointer in the entry

Assignees

• Intel Corp

Inventors

• Kumar Sanjay
• Lantz Philip R
• Sankaran Rajesh M
• Neiger Gilbert
• Vakharwala Rupin H

Classifications

• G06F2009/45579

  I/O management, e.g. providing access to device drivers or storage · CPC title

• G06F13/24

  using interrupt (G06F13/32 takes precedence) · CPC title

• G06F9/542

  Event management; Broadcasting; Multicasting; Notifications · CPC title

• G06F9/45558 Primary

  Hypervisor-specific management and integration aspects · CPC title

• G06F9/4812 Primary

  by interrupt, e.g. masked · CPC title