Virtual processor direct interrupt delivery mechanism

Patent metadata

Field	Value
Publication number	US-9910699-B2
Application number	US-201414525959-A
Country	US
Kind code	B2
Filing date	Oct 28, 2014
Priority date	Oct 28, 2014
Publication date	Mar 6, 2018
Grant date	Mar 6, 2018

Abstract

A method comprising is described. The method includes receiving an interrupt targeting a virtual processor, determining a status of the virtual processor and directly delivering the interrupt to the virtual processor upon determining that the virtual processor is operating in a running state.

First claim

What is claimed is:

1. A method of processing external interrupts for virtual processors using a host processor, the method comprising:
configuring a virtual machine monitor (VMM) in a host processor, the host processor having at least one logical processor and the VMM controlling a plurality of virtual processors for the at least one logical processor, the controlling including:
allocating at least two physical interrupt vectors in the host processor, including a running notification vector (RNV) for posting interrupts to running virtual processors and a blocked notification vector (BNV) for posting interrupts to blocked virtual processors;
masking interrupts posted to preempted virtual processors, the preempted virtual processors including previously blocked virtual processors having at least one posted interrupt and previously running virtual processors; and
enabling delivery of notifications for masked interrupts using the RNV upon transitioning a preempted virtual processor to a running virtual processor.

2. The method of claim 1 , wherein enabling delivery of notifications for masked interrupts using the RNV includes:
issuing a self inter-processor interrupt (self-IPI) to the VMM;
detecting the self-IPI at the host processor upon transitioning a preempted virtual processor into a running virtual processor;
performing posted interrupt processing at the host processor upon detecting the self-IPI, including moving any masked interrupts to the virtual interrupt controller for delivery of notifications.

3. The method of claim 1 , further comprising:
receiving a notification event from the BNV for a blocked virtual processor; and
transitioning the blocked virtual processor into a preempted virtual processor.

4. The method of claim 1 , further comprising:
migrating interrupts posted for preempted virtual processors being migrated to a new destination logical processor, including updating any posted interrupts for the migrated virtual processors to a new destination interrupt controller for the new destination logical processor; and
queueing the migrated virtual processors to the preempted list of preempted virtual processors on the new destination logical processor.

Assignees

• Sankaran Rajesh M
• Neiger Gilbert
• Intel Corp

Inventors

• Sankaran Rajesh M
• Neiger Gilbert

Classifications

• G06F9/45533

  Hypervisors; Virtual machine monitors · CPC title

• G06F13/24

  using interrupt (G06F13/32 takes precedence) · CPC title

• G06F9/4812 Primary

  by interrupt, e.g. masked · CPC title