Posted interrupt architecture

Patent metadata

Field	Value
Publication number	US-2016147679-A1
Application number	US-201414553430-A
Country	US
Kind code	A1
Filing date	Nov 25, 2014
Priority date	Nov 25, 2014
Publication date	May 26, 2016
Grant date	—

Abstract

An interrupt is identified from an input/output (I/O) device and an address of a particular cache line is identified associated with the interrupt. The cache line corresponds to a destination of the interrupt and represents one or more attributes of the interrupt. A request is sent to a coherency agent to acquire ownership of the particular cache line and a request is sent to perform a read-modify-write (RMW) operation on the cache line based on the interrupt.

First claim

What is claimed is:

1 . An apparatus comprising:
a protocol agent to:
identify an interrupt from an input/output (I/O) device;
identify an address of a particular cache line associated with the interrupt, wherein the particular cache line is to correspond to a destination of the interrupt and the particular cache line is to represent one or more attributes of the interrupt;
send a request to a coherency agent to acquire ownership of the particular cache line; and
send a request to perform a read-modify-write (RMW) operation on the cache line based on the interrupt.

2 . The apparatus of claim 1 , wherein the protocol agent is further to:
receive information read from the particular cache line; and determine whether to forward the physical interrupt to the destination based on the information.

3 . The apparatus of claim 2 , wherein the information is read from the particular cache line by the coherency agent and the information is received from the coherency agent in association with the RMW operation.

4 . The apparatus of claim 2 , wherein the destination comprises a virtual resource hosted by a physical processor and the physical interrupt is to be sent to the physical processor.

5 . The apparatus of claim 4 , wherein the physical processor is to be identified from the information.

6 . The apparatus of claim 4 , wherein the virtual resource comprises a virtual processor.

7 . The apparatus of claim 1 , wherein the particular cache line is one of a plurality of posted interrupt descriptor cache lines and each posted interrupt descriptor cache line corresponds to a respective one of a plurality of interrupt destinations and each interrupt destination comprises a virtual resource.

8 . The apparatus of claim 1 , wherein the protocol agent is to enforce ordering rules of a protocol in association with handling of the interrupt.

9 . The apparatus of claim 1 , wherein the protocol agent and coherency agent are included in a root complex and the root complex receives the interrupt.

10 . An apparatus comprising:
an address translator to determine an entry in an interrupt remapping table associated with an interrupt identifier, wherein the entry comprises an address of a particular cache line, the particular cache line to correspond to a destination of the interrupt, and the particular cache line is to describe attributes of the interrupt; a coherence agent to obtain ownership of the particular cache line and initiate a read-modify-write (RMW) operation on the particular cache line; a protocol agent to identify one or more characteristics of the interrupt and request the coherence agent to perform a RMW operation, wherein the particular cache line is to describe the one or more characteristics; and decision logic to determine whether to forward the interrupt based on information to be included in the particular cache line.

11 . The apparatus of claim 11 , wherein the decision logic is included in the protocol agent.

12 . The apparatus of claim 12 , wherein the protocol interrupt remapping table maps addresses in a guest domain to an address in a host domain.

13 . The apparatus of claim 11 , wherein the protocol agent is to identify the handle and query the address translator for the address.

14 . The apparatus of claim 11 , wherein the information comprises a suppress value and a pending value of the particular cache line.

15 . The apparatus of claim 11 , wherein ordering rules of a particular protocol are to be enforced using the protocol agent and the particular protocol comprises a Peripheral Component Interconnect (PCI) Express (PCIe)-based protocol.

16 . A computer readable medium comprising code that, when executed, is to cause a computing device to:
identify an interrupt from an I/O device; identify an address of a particular posted interrupt descriptor cache line, wherein the posted interrupt descriptor cache line corresponds to a destination of the interrupt and the posted interrupt descriptor cache line is to describe the interrupt; send a request to a coherence agent to acquire ownership of the particular posted interrupt descriptor cache line; and send a request to perform a read-modify-write (RMW) operation on the posted interrupt descriptor cache line based on the interrupt.

17 . The medium of claim 16 , wherein identifying the address of the particular posted interrupt descriptor cache line comprises:
identifying a handle value included in the interrupt; and querying a remapping table to determine a particular address corresponding to the handle, wherein the particular address comprises the address of the particular posted interrupt descriptor cache line.

18 . A system comprising:
a processor; a memory; and a root complex comprising:
an agent to:
identify an interrupt addressed to a destination;
identify an address of a particular cache line, wherein the cache line corresponds to the destination and the cache line is to be encoded to describe the interrupt;
send a request to a coherence agent to acquire ownership of the particular cache line; and
send a request to perform a read-modify-write (RMW) operation on the cache line based on the interrupt.

19 . The system of claim 18 , wherein the destination comprises a particular one of a plurality of virtual processors and the system further comprises a virtual machine manager.

20 . The system of claim 19 , further comprising one or more I/O devices, wherein the interrupt is received from one of the I/O devices and is intended for a particular one of the plurality of virtual processors.

Assignees

• Intel Corp

Inventors

• Guddeti Jayakrishna
• Chang Luke
• Sankaran Rajesh M
• Thaliyil Junaid F

Classifications

• G06F12/0871

  Allocation or management of cache space · CPC title

• G06F2212/1032

  Reliability improvement, data loss prevention, degraded operation etc · CPC title

• G06F13/24 Primary

  using interrupt (G06F13/32 takes precedence) · CPC title

• G06F12/0813

  with a network or matrix configuration · CPC title

• G06F2009/45579

  I/O management, e.g. providing access to device drivers or storage · CPC title