Delivering interrupts to user-level applications

Patent metadata

Field	Value
Publication number	US-9921984-B2
Application number	US-201414581677-A
Country	US
Kind code	B2
Filing date	Dec 23, 2014
Priority date	Dec 23, 2014
Publication date	Mar 20, 2018
Grant date	Mar 20, 2018

Abstract

Systems and methods for delivering interrupts to user-level applications. An example processing system comprises: a memory configured to store a plurality of user-level APIC data structures and a plurality of user-level interrupt handler address data structures corresponding to a plurality of user-level applications being executed by the processing system; and a processing core configured, responsive to receiving a notification of a user-level interrupt, to: set a pending interrupt bit flag having a position defined by an identifier of the user-level interrupt in a user-level APIC data structure associated with a user-level application that is currently being executed by the processing core, and invoke a user-level interrupt handler identified by a user-level interrupt handler address data structure associated with the user-level application, for a pending user-level interrupt having a highest priority among one or more pending user-level interrupts identified by the user-level APIC data structure.

First claim

What is claimed is:

1. A processing system, comprising:
a memory configured to store a plurality of user-level Advanced Programmable Interrupt Controller (APIC) data structures and a plurality of user-level interrupt handler address data structures corresponding to a plurality of user-level applications being executed by the processing system; and
a processing core configured, responsive to receiving a notification of an interrupt, to:
responsive to ascertaining that an identifier of the interrupt matches a notification interrupt vector associated with a user-level application that is currently being executed by the processing core, determine that the interrupt is processed as a user-level interrupt,
set, in a user-level APIC data structure associated with the user-level application, a pending interrupt bit flag having a position matching a position of a bit flag set in a posted interrupt descriptor data structure associated with the user-level application, and
invoke a user-level interrupt handler identified by a user-level interrupt handler address data structure associated with the user-level application, for a pending user-level interrupt having a highest priority among one or more pending user-level interrupts identified by the user-level APIC data structure.

2. The processing system of claim 1 , wherein the processing core is further configured, responsive to setting the pending interrupt bit flag, to trigger a micro-architectural event indicating presence of a pending user-level interrupt.

3. The processing system of claim 2 , wherein the processing core is configured to invoke the user-interrupt handler responsive to detecting the micro-architectural event indicating presence of the pending user-level interrupt.

4. The processing system of claim 1 , wherein each user-level APIC data structure of the plurality of user-level APIC data structures includes a bitmap comprising plurality of pending interrupt bits, wherein a position of each bit within the bitmap corresponds to an interrupt identifier.

5. The processing system of claim 1 , wherein each user-level interrupt handler address data structure comprises a table of addresses of user-level interrupt handlers indexed by an interrupt identifier.

6. The processing system of claim 1 , wherein each user-level interrupt handler address data structure comprises an address of a single interrupt handler for multiple types of user-level interrupts to be processed by a user-level application associated with the user-level interrupt handler address data structure.

7. The processing system of claim 1 , further comprising a processing logic configured to:
responsive to identifying an incoming interrupt as a user-level interrupt, identify an address of the posted interrupt descriptor data structure associated with the user-level application that is currently being executed by the processing core;
set a bit corresponding to an identifier of the interrupt in a bitmap associated with the posted interrupt descriptor data structure; and
transmit a notification interrupt having an interrupt number identified by the posted interrupt descriptor data structure.

8. The processing system of claim 1 , wherein invoking the user-level interrupt handler further comprises:
storing a current value of an instruction pointer on a stack; and
loading an address of the user-level interrupt handler into the instruction pointer.

9. The processing system of claim 1 , wherein the processing system is represented by a System-on-Chip (SoC).

10. A method, comprising:
receiving a notification of an interrupt;
responsive to ascertaining that an identifier of the interrupt matches a notification interrupt vector associated with a user-level application that is currently being executed by the processing core, determining that the interrupt is processed as a user-level interrupt;
setting, in a user-level APIC data structure associated with the user-level application, a pending interrupt bit having a position matching a position of a bit flag set in a posted interrupt descriptor data structure associated with the user-level application;
identifying, using the user-level APIC data structure, a pending user-level interrupt having a highest priority among one or more pending user-level interrupts; and
identifying, using a user-level interrupt handler address data structure associated with the user-level application, an interrupt handler for the identified user-level interrupt.

11. The method of claim 10 , further comprising:
responsive to setting the pending interrupt bit flag, triggering a micro-architectural event indicating presence of a pending user-level interrupt.

12. The method of claim 11 , further comprising:
invoking the identified user-interrupt handler responsive to detecting the micro-architectural event indicating presence of the pending user-level interrupt.

13. The method of claim 12 , wherein invoking the user-level interrupt handler further comprises:
storing a current value of an instruction pointer on a stack; and
loading an address of the user-level interrupt handler into the instruction pointer.

14. The method of claim 10 , wherein each user-level APIC data structure of the plurality of user-level APIC data structures includes a bitmap comprising plurality of pending interrupt bits, wherein a position of each bit within the bitmap corresponds to an interrupt identifier.

15. The method of claim 10 , wherein each user-level interrupt handler address data structure comprises a table of addresses of user-level interrupt handlers indexed by an interrupt identifier.

16. The method of claim 10 , wherein each user-level interrupt handler address data structure comprises an address of a single interrupt handler for multiple types of user-level interrupts to be processed by a user-level application associated with the user-level interrupt handler address data structure.

17. The method of claim 10 , further comprising:
responsive to identifying an incoming interrupt as a user-level interrupt, identifying an address of the posted interrupt descriptor data structure associated with the user-level application that is currently being executed by the processing core;
setting a bit corresponding to an identifier of the interrupt in a bitmap associated with the posted interrupt descriptor data structure; and
transmitting a notification interrupt having an interrupt number identified by the posted interrupt descriptor data structure.

18. A computer-readable non-transitory storage medium comprising executable instructions that, when executed by a processing system, cause the processing system to perform operations, comprising:
receiving a notification of an interrupt;
responsive to ascertaining that an identifier of the interrupt matches a notification interrupt vector associated with a user-level application that is currently being executed by the processing core, determining that the interrupt is processed as a user-level interrupt;
setting, in a user-level APIC data structure associated with the user-level application, a pending interrupt bit having a position matching a position of a bit flag set in a posted interrupt descriptor data structure associated with the user-level application;
identifying, using the user-level APIC data structure, a pending user-level interrupt having a highest priority among one or more pending user-level interrupts; and
identifying, using a user-level interrupt handler address data structure associated with the user-level application, an interrupt handler for the identified user-level

Assignees

• Intel Corp

Inventors

• Neiger Gilbert
• Sankaran Rajesh M

Classifications

• G06F13/34 Primary

  with priority control · CPC title

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title