Delivering interrupts to user-level applications

Patent metadata

Field	Value
Publication number	US-11113217-B2
Application number	US-202016778227-A
Country	US
Kind code	B2
Filing date	Jan 31, 2020
Priority date	Dec 23, 2014
Publication date	Sep 7, 2021
Grant date	Sep 7, 2021

Abstract

Systems and methods for delivering interrupts to user-level applications. An example processing system comprises: a memory configured to store a plurality of user-level APIC data structures and a plurality of user-level interrupt handler address data structures corresponding to a plurality of user-level applications being executed by the processing system; and a processing core configured, responsive to receiving a notification of a user-level interrupt, to: set a pending interrupt bit flag having a position defined by an identifier of the user-level interrupt in a user-level APIC data structure associated with a user-level application that is currently being executed by the processing core, and invoke a user-level interrupt handler identified by a user-level interrupt handler address data structure associated with the user-level application, for a pending user-level interrupt having a highest priority among one or more pending user-level interrupts identified by the user-level APIC data structure.

First claim

What is claimed is:

1. A processing system, comprising:
a memory to store an interrupt control data structure associated with an application being executed by the processing system; and
a processing core to, without a privilege level transition:
determine that an identifier of a pending interrupt matches a notification interrupt vector associated with the application,
set, in the interrupt control data structure, a pending interrupt flag corresponding to an identifier of the interrupt,
select a highest priority pending interrupt among pending interrupts identified by the interrupt control data structure, and
invoke an interrupt handler for the highest priority pending interrupt identified by the interrupt control data structure.

2. The processing system of claim 1 , wherein the processing core is further to:
responsive to setting the pending interrupt flag, trigger a micro-architectural event indicating pendency of the user-level interrupt.

3. The processing system of claim 2 , wherein the processing core is further to:
invoke the interrupt handler responsive to detecting the micro-architectural event.

4. The processing system of claim 1 , wherein the interrupt control data structure includes a bitmap comprising plurality of pending interrupt bits, wherein a position of each bit within the bitmap corresponds to an interrupt identifier.

5. The processing system of claim 1 , further comprising a processing logic to:
responsive to identifying an incoming interrupt as a user-level interrupt, identify an address of a posted interrupt descriptor associated with the application;
set, in the posted interrupt descriptor data structure, a flag corresponding to an identifier of the incoming interrupt; and
transmit a notification interrupt having an interrupt number identified by the posted interrupt descriptor.

6. The processing system of claim 1 , wherein invoking the interrupt handler further comprises:
storing a current value of an instruction pointer on a stack; and
loading an address of the interrupt handler into the instruction pointer.

7. The processing system of claim 1 , wherein the processing system is represented by a System-on-Chip (SoC).

8. The processing system of claim 1 , wherein the notification interrupt vector is identified by a pre-defined field of a posted interrupt descriptor data structure associated with the user-level application.

9. A method, comprising:
determining, by a processing core without a privilege level transition, that an identifier of a pending interrupt matches a notification interrupt vector associated with an application being executed by the processing core;
setting, in an interrupt control data structure associated with the application, a pending interrupt flag corresponding to an identifier of the interrupt;
selecting a highest priority pending interrupt among pending interrupts identified by the interrupt control data structure; and
invoking an interrupt handler for the highest priority pending interrupt identified by the interrupt control data structure.

10. The method of claim 9 , further comprising:
responsive to setting the pending interrupt flag, triggering a micro-architectural event indicating pendency of the user-level interrupt.

11. The method of claim 10 , further comprising:
invoking the interrupt handler responsive to detecting the micro-architectural event.

12. The method of claim 9 , wherein invoking the user-level interrupt handler further comprises:
storing a current value of an instruction pointer on a stack; and
loading an address of the interrupt handler into the instruction pointer.

13. The method of claim 9 , wherein the interrupt control data structure includes a bitmap comprising plurality of pending interrupt bits, wherein a position of each bit within the bitmap corresponds to an interrupt identifier.

14. The method of claim 9 , further comprising:
responsive to identifying an incoming interrupt as a user-level interrupt, identifying an address of a posted interrupt descriptor associated with the application;
setting, in the posted interrupt descriptor data structure, a flag corresponding to an identifier of the incoming interrupt; and
transmitting a notification interrupt having an interrupt number identified by the posted interrupt descriptor.

15. The method of claim 9 , wherein the notification interrupt vector is identified by a pre-defined field of a posted interrupt descriptor data structure associated with the user-level application.

16. A computer-readable non-transitory storage medium comprising executable instructions that, when executed by a processing system, cause the processing system to:
determine, without a privilege level transition, that an identifier of a pending interrupt matches a notification interrupt vector associated with an application being executed by the processing system;
set, in an interrupt control data structure associated with the application, a pending interrupt flag corresponding to an identifier of the interrupt;
selecting a highest priority pending interrupt among pending interrupts identified by the interrupt control data structure; and
invoke an interrupt handler for the highest priority pending interrupt identified by the interrupt control data structure.

17. The computer-readable non-transitory storage medium of claim 16 , wherein the notification interrupt vector is identified by a pre-defined field of a posted interrupt descriptor data structure associated with the user-level application.

18. The computer-readable non-transitory storage medium of claim 16 , wherein the interrupt control data structure includes a bitmap comprising plurality of pending interrupt bits, wherein a position of each bit within the bitmap corresponds to an interrupt identifier.

19. The computer-readable non-transitory storage medium of claim 16 , further comprising executable instructions that, when executed by the processing system, cause the processing system to:
responsive to identifying an incoming interrupt as a user-level interrupt, identifying an address of a posted interrupt descriptor associated with the application;
setting, in the posted interrupt descriptor data structure, a flag corresponding to an identifier of the incoming interrupt; and
transmitting a notification interrupt having an interrupt number identified by the posted interrupt descriptor.

Assignees

• Intel Corp

Inventors

• Neiger Gilbert
• Sankaran Rajesh M

Classifications

• G06F13/34 Primary

  with priority control · CPC title

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title