Semiconductor devices including source/drain layers and methods of manufacturing the same

Patent metadata

Field	Value
Publication number	US-12495578-B2
Application number	US-202217656023-A
Country	US
Kind code	B2
Filing date	Mar 23, 2022
Priority date	Jun 30, 2021
Publication date	Dec 9, 2025
Grant date	Dec 9, 2025

Abstract

A semiconductor device includes first and second channels, first and second gate structures, first and second source/drain layers, first and second fin spacers, and first and second etch stop patterns. The first channels are disposed vertically on a first region of a substrate. The second channels are disposed vertically on a second region of the substrate. The first gate structure is formed on the first region and covers the first channels. The second gate structure is formed on the second region and covers the second channels. The first and second source/drain layers contact the first and second channels, respectively. The first and second fin spacers contact sidewalls and upper surfaces of the first and second source/drain layers, respectively. The first and second etch stop patterns are formed on the first and second fin spacers, respectively, and do not contact the first and second source/drain layers, respectively.

First claim

What is claimed is:

1 . A semiconductor device, comprising:
a plurality of first channels disposed on a first region of a substrate, the substrate including the first region and a second region, and each of the plurality of first channels being spaced apart from each other in a vertical direction that is substantially perpendicular to an upper surface of the substrate; a plurality of second channels disposed on the second region of the substrate and spaced apart from each other in the vertical direction; a first gate structure disposed on the first region of the substrate, the first gate structure covering at least a portion of each of the plurality of first channels; a second gate structure disposed on the second region of the substrate, the second gate structure covering at least a portion of each of the plurality of second channels; a first source/drain layer disposed on a portion of the first region of the substrate that is adjacent to the first gate structure, the first source/drain layer directly contacting the plurality of first channels; a second source/drain layer disposed on a portion of the second region of the substrate that is adjacent to the second gate structure, the second source/drain layer directly contacting the plurality of second channels; a first fin spacer directly contacting a sidewall and an upper surface of the first source/drain layer; a second fin spacer directly contacting a sidewall and an upper surface of the second source/drain layer; a first etch stop pattern disposed on the first fin spacer, the first etch stop pattern not directly contacting the first source/drain layer; and a second etch stop pattern disposed on the second fin spacer, the second etch stop pattern not directly contacting the second source/drain layer, wherein an upper portion of the first source/drain layer has a first cross-section having a shape of a pentagon or a hexagon, and an upper portion of the second source/drain layer has a second cross-section having a shape of a rectangle with rounded corners, and wherein each of the first and second fin spacers includes a low-k dielectric material, and each of the first and second etch stop patterns includes silicon nitride.

2 . The semiconductor device of claim 1 , wherein each of the first and second fin spacers includes silicon oxycarbonitride, silicon oxynitride, and/or silicon carbonitride.

3 . The semiconductor device of claim 1 , wherein the first source/drain layer includes a semiconductor material doped with p-type impurities, and the second source/drain layer includes a semiconductor material doped with n-type impurities.

4 . The semiconductor device of claim 1 , further comprising:
a first active pattern disposed on the first region of the substrate and extending in a first direction substantially parallel to the upper surface of the substrate; a second active pattern disposed on the second region of the substrate and extending in the first direction; and an isolation pattern disposed on the substrate, the isolation pattern covering sidewalls of the first and second active patterns, wherein each of the plurality of first channels and the first source/drain layer are formed on the first active pattern, and each of the plurality of second channels and the second source/drain layer are formed on the second active pattern.

5 . The semiconductor device of claim 4 , wherein the first fin spacer covers an upper surface of the first source/drain layer and opposite sidewalls of the first source/drain layer in a second direction substantially parallel to the upper surface of the substrate and crossing the first direction, and contacts an upper surface of a portion of the isolation pattern adjacent to the first source/drain layer in the second direction, and
wherein the second fin spacer covers an upper surface of the second source/drain layer and opposite sidewalls of the second source/drain layer in the second direction, and contacts an upper surface of a portion of the isolation pattern adjacent to the second source/drain layer in the second direction.

6 . The semiconductor device of claim 4 , wherein the first gate structure extends on the first active pattern and the isolation pattern in a second direction substantially parallel to the upper surface of the substrate and crossing the first direction, and the second gate structure extends on the second active pattern and the isolation pattern in the second direction, and
wherein the semiconductor device further comprises: a first gate spacer covering each of a pair of opposite sidewalls in the first direction of the first gate structure; and a second gate spacer covering each of a pair of opposite sidewalls in the first direction of the second gate structure.

7 . The semiconductor device of claim 6 , wherein the first gate spacer includes a same material as the first fin spacer and is connected thereto, and the second gate spacer includes a same material as the second fin spacer and is connected thereto.

8 . The semiconductor device of claim 6 , wherein a portion of the first gate spacer overlapping the first source/drain layer in the first direction has a lowermost surface that is lower than an uppermost surface of the first source/drain layer, and a portion of the second gate spacer overlapping the second source/drain layer in the first direction has a lowermost surface that is lower than an uppermost surface of the second source/drain layer.

9 . The semiconductor device of claim 6 , wherein the first etch stop pattern covers a sidewall of the first gate spacer, and the second etch stop pattern covers a sidewall of the second gate spacer.

10 . The semiconductor device of claim 1 , wherein the semiconductor device further comprises:
a first gate spacer covering at least a portion of each of a pair of opposite sidewalls of the first gate structure; and a second gate spacer covering at least a portion of each of a pair of opposite sidewalls of the second gate structure, wherein the first gate spacer is integral with the first fin spacer, and the second gate spacer is integral with the second fin spacer.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Yu Haejun
• Choi Kyungin
• Kim Sungmin
• Lee Seunghun
• Kim Jinbum

Classifications

• H10D84/85 Primary

  Complementary IGFETs, e.g. CMOS · CPC title

• H10D64/258

  characterised by the relative positions of the source or drain electrodes with respect to the gate electrode · CPC title

• H10D62/118

  Nanostructure semiconductor bodies · CPC title

• H10D30/6757

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title

• H10D64/017

  using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes · CPC title