Low-k gate spacer and methods for forming the same

Patent metadata

Field	Value
Publication number	US-10490650-B2
Application number	US-201715812966-A
Country	US
Kind code	B2
Filing date	Nov 14, 2017
Priority date	Nov 14, 2017
Publication date	Nov 26, 2019
Grant date	Nov 26, 2019

Abstract

Embodiments of the present disclosure relate to a FinFET device having gate spacers with reduced capacitance and methods for forming the FinFET device. Particularly, the FinFET device according to the present disclosure includes gate spacers formed by two or more depositions. The gate spacers are formed by depositing first and second materials at different times of processing to reduce parasitic capacitance between gate structures and contacts introduced after epitaxy growth of source/drain regions.

First claim

What is claimed is:

1. A method, comprising:
forming a first dielectric layer over a fin structure and a dummy gate stack, the dummy gate stack being over the fin structure;
conformally depositing a sacrificial layer over the first dielectric layer;
performing an etch process to expose portions of the fin structure while sidewalls of the dummy gate stack remain covered by the sacrificial layer and the first dielectric layer;
growing source/drain regions from the exposed portions of the fin structure;
after growing the source/drain regions, removing the sacrificial layer to expose the first dielectric layer; and
depositing a second dielectric layer on the first dielectric layer.

2. The method of claim 1 , wherein the second dielectric layer includes a dielectric material having a dielectric constant (k) value equal to or less than 3.9.

3. The method of claim 1 , wherein the second dielectric layer comprises silicon oxycarbide (SiOC), silicon oxycarbonnitride (SiOCN), or a combination thereof.

4. The method of claim 1 , wherein the second dielectric layer is a porous film having a porosity in a range between 2.00% to 3.50%.

5. The method of claim 1 , wherein the first dielectric layer includes silicon nitride (SiN), silicon oxycarbide (SiOC), silicon oxycarbonnitride (SiOCN), or a combination thereof.

6. The method of claim 1 , wherein the first dielectric layer has a thickness in a range from 10 angstroms to 30 angstroms, and the second dielectric layer has a thickness in a range from 20 angstroms to 40 angstroms.

7. A structure, comprising:
a fin structure having source/drain regions on a substrate;
a metal gate structure between the source/drain regions on the fin structure, wherein the metal gate structure includes:
a conformal high-k dielectric layer over the fin structure; and
a gate electrode over the conformal high-k dielectric layer;

a first gate spacer along a sidewall of the metal gate structure; and
a second gate spacer along the first gate spacer and over the source/drain regions of the fin structure, wherein the first gate spacer is disposed between the metal gate structure and the second gate spacer.

8. The structure of claim 7 , wherein the second gate spacer includes a dielectric material having a dielectric constant (k) value equal to or less than 3.9.

9. The structure of claim 7 , wherein the second gate spacer comprises silicon oxycarbide (SiOC), silicon oxycarbonnitride (SiOCN), or a combination thereof.

10. The structure of claim 7 , wherein the second gate spacer is a porous film having a porosity in a range from 2.00% to 3.50%.

11. The structure of claim 7 , wherein the first gate spacer includes silicon nitride (SiN), silicon oxycarbide (SiOC), silicon oxycarbonnitride (SiOCN), or a combination thereof.

12. The structure of claim 7 , wherein the first gate spacer has a thickness in a range from 10 angstroms to 30 angstroms, and the second gate spacer has a thickness in a range from 20 angstroms to 40 angstroms.

13. A method, comprising:
forming a dummy gate stack over a fin structure;
forming a first spacer layer over the fin structure and the dummy gate stack;
depositing a sacrificial layer over the first spacer layer;
recessing the fin structure on both sides of the dummy gate stack;
growing source/drain regions from the recessed fin structure;
removing the sacrificial layer to expose the first spacer layer; and
depositing a second spacer layer over the first spacer layer, the source/drain region, and the dummy gate stack;
depositing a contact etch stop layer over the second spacer layer;
removing the dummy gate stack to form a recess between remaining portions of the first spacer layer; and
forming a metal gate stack in the recess.

14. The method of claim 13 , wherein growing the source/drain regions comprises epitaxially growing the source/drain regions from the fin structure.

15. The method of claim 13 , wherein recessing the fin structure comprises etching the sacrificial layer and the first spacer layer anisotropically to expose portions of the fin structure while sidewalls of the dummy gate stack remain covered by the first spacer layer.

16. The method of claim 15 , wherein recessing the fin structure comprises removing the sacrificial layer and the first spacer layer from sidewalls and a top surface of the fin structure.

17. The method of claim 15 , wherein recessing the fin structure comprises removing portions of the fin structure on opposite sides of the dummy gate stack.

18. The method of claim 17 , wherein recessing the fin structure comprises leaving portions of the first spacer layer that is deposited on sidewalls of the fin structure, and forming a recess between the portions of the first spacer layer.

19. The method of claim 15 , wherein the second spacer layer comprises silicon oxycarbide (SiOC), silicon oxycarbonnitride (SiOCN), or a combination thereof.

20. The method of claim 15 , wherein the second spacer layer includes a dielectric material having a dielectric constant (k) value equal to or less than 3.9.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Lin Wen-Kai
• Lai Bo-Yu
• Te Li Chun
• LEE Kai-Hsuan
• Yeong Sai-Hooi
• Bao Tien-I
• Lin Wei-Ken

Classifications

• H01L21/823864

  Electricity · mapped topic

• H01L21/823814

  Electricity · mapped topic

• H01L21/823821

  Electricity · mapped topic

• H01L29/66795

  Electricity · mapped topic

• H01L29/66636

  Electricity · mapped topic