Gate-all-around structure and methods of forming the same

Patent metadata

Field	Value
Publication number	US-10923598-B2
Application number	US-201916511176-A
Country	US
Kind code	B2
Filing date	Jul 15, 2019
Priority date	Nov 27, 2018
Publication date	Feb 16, 2021
Grant date	Feb 16, 2021

Abstract

Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary method comprises forming a fin over a substrate, wherein the fin comprises a first semiconductor layer and a second semiconductor layer including different semiconductor materials, and the fin comprises a channel region and a source/drain region; forming a dummy gate structure over the channel region of the fin and over the substrate; etching a portion of the fin in the source/drain region to form a trench therein, wherein a bottom surface of the trench is below a bottom surface of the second semiconductor layer; selectively removing an edge portion of the second semiconductor layer in the channel region such that the second semiconductor layer is recessed; forming a sacrificial structure around the recessed second semiconductor layer and over the bottom surface of the trench; and epitaxially growing a source/drain feature in the source/drain region of the fin.

First claim

What is claimed is:

1. A method of forming a semiconductor device, comprising:
forming a fin over a substrate, wherein the fin comprises first semiconductor layers and second semiconductor layers including different semiconductor materials, and the fin comprises a channel region and a source/drain region;
forming a dummy gate structure over the channel region of the fin and over the substrate;
etching a portion of the fin in the source/drain region to form a trench therein, wherein a bottom surface of the trench is below a bottom surface of a lowermost second semiconductor layer of the fin;
selectively removing edge portions of the second semiconductor layers in the channel region such that the second semiconductor layers are recessed;
forming a sacrificial structure around the recessed second semiconductor layers and over the bottom surface of the trench; and
epitaxially growing a source/drain feature in the source/drain region of the fin.

2. The method of claim 1 , further comprising:
selectively removing the sacrificial structure to form a gap between the source/drain feature and the recessed second semiconductor layers and to form a gap between the source/drain feature and the substrate; and
forming inner spacers to fill in the gap between the source/drain feature and the recessed second semiconductor layers and the gap between the source/drain feature and the substrate.

3. The method of claim 1 , further comprising performing an oxidation process to the sacrificial structure to form inner spacers.

4. The method of claim 3 , wherein the oxidation process is a dry oxidation process.

5. The method of claim 4 , wherein the dry oxidation process is performed at a temperature of about 400 degrees Celsius and about 600 degrees Celsius.

6. The method of claim 4 , wherein the dry oxidation process is performed for about 30 minutes to about 120 minutes.

7. The method of claim 1 , wherein a semiconductor material of the sacrificial structure has a different etch selectivity or a different oxidation rate than the first semiconductor layers and the second semiconductor layers.

8. The method of claim 1 , wherein the sacrificial structure and the first semiconductor layers form a continuous surface of the source/drain region of the fin before epitaxially growing the source/drain feature.

9. The method of claim 1 , further comprising:
removing the dummy gate structure to expose the channel region of the fin;
selectively etching the second semiconductor layers Currently amended in the channel region of the fin; and
forming a metal gate structure over the channel region of the fin.

10. A method of forming a semiconductor device, comprising:
forming a fin over a substrate, wherein the fin comprises a first semiconductor layer and a second semiconductor layer including different semiconductor materials;
forming a dummy gate structure over the substrate and the fin to define a channel region and a source/drain region of the fin;
etching a portion of the first semiconductor layer and the second semiconductor layer in the source/drain region of the fin to form a trench;
selectively removing a portion of the second semiconductor layer in the channel region of the fin such that the second semiconductor layer is recessed;
forming a sacrificial structure in the trench to cover the recessed second semiconductor layer and the bottom surface of the trench;
epitaxially growing a source/drain feature in the source/drain region of the fin; and
forming an inner spacer to replace the sacrificial structure.

11. The method of claim 10 , wherein forming the sacrificial structure comprises:
epitaxially growing a sacrificial layer in the trench; and
etching the sacrificial layer to expose sidewalls of the first semiconductor layer.

12. The method of claim 10 , wherein forming the inner spacer comprises:
removing the sacrificial structure to form a gap between the source/drain feature and the second semiconductor layer and to form a gap between the source/drain feature and the substrate; and
forming the inner spacer to fill in the gap between the source/drain feature and the second semiconductor layer and the gap between the source/drain feature and the substrate.

13. The method of claim 10 , wherein forming the inner spacer comprises:
performing an oxidation process to the sacrificial structure to form the inner spacer.

14. The method of claim 10 , wherein a bottom surface of the trench is below a bottom surface of the second semiconductor layer about 5 nanometers to about 20 nanometers.

15. The method of claim 10 , wherein a height of the sacrificial structure over the bottom surface of the trench is about 10 nanometers to about 30 nanometers.

16. The method of claim 10 , wherein a semiconductor material of the sacrificial structure has a different etch selectivity or a different oxidation rate than the first semiconductor layer and the second semiconductor layer.

17. The method of claim 10 , wherein:
the first semiconductor layer of the fin comprises silicon (Si);
the second semiconductor layer of the fin comprises silicon germanium (SiGe), wherein a molar ratio of germanium (Ge) is about 20% to about 40%; and
the sacrificial structure comprises SiGe, wherein a molar ratio of germanium (Ge) is more than about 45%.

18. The method of claim 10 , wherein the sacrificial structure and the first semiconductor layer form a continuous surface of the source/drain region of the fin before epitaxially growing the source/drain feature.

19. A semiconductor device, comprising:
a fin disposed over a substrate, wherein the fin comprises a channel region and a source/drain region;
a gate structure disposed over the substrate and wrapping around the channel region of the fin;
a source/drain feature epitaxially grown in the source/drain region of the fin; and
a dielectric inner spacer disposed between the source/drain feature and the gate structure and between the source/drain feature and the substrate, wherein a bottom surface of the dielectric inner spacer is below a bottom surface of the gate structure.

20. The semiconductor device of claim 19 , wherein a height of the inner spacer between the source/drain feature and the substrate is about 10 nanometers to about 30 nanometers.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Wang Pei-Hsun
• Lin Chun-Hsiung
• Wang Chih-Hao

Classifications

• H10P50/642

  Chemical etching · CPC title

• H10P14/6308

  of Group IV semiconductors · CPC title

• H10P14/3462

  Nanowires · CPC title

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title

• H10D64/018

  Spacers formed inside holes at the prospective gate locations, e.g. holes left by removing dummy gates · CPC title