Semiconductor devices

Patent metadata

Field	Value
Publication number	US-11038018-B2
Application number	US-202016775513-A
Country	US
Kind code	B2
Filing date	Jan 29, 2020
Priority date	May 14, 2019
Publication date	Jun 15, 2021
Grant date	Jun 15, 2021

Abstract

A semiconductor device includes an active pattern on a substrate, the active pattern extending in a first direction parallel to an upper surface of the substrate, a gate structure on the active pattern, the gate structure extending in a second direction parallel to the upper surface of the substrate and crossing the first direction, channels spaced apart from each other in a third direction perpendicular to the upper surface of the substrate, each of the channels extending through the gate structure, a source/drain layer on a portion of the active pattern adjacent the gate structure, the source/drain layer contacting the channels, and a sacrificial pattern on an upper surface of each of opposite edges of the portion of the active pattern in the second direction, the sacrificial pattern contacting a lower portion of a sidewall of the source/drain layer and including silicon-germanium.

First claim

What is claimed is:

1. A semiconductor device, comprising:
an active pattern on a substrate, the active pattern extending in a first direction parallel to an upper surface of the substrate;
a gate structure on the active pattern, the gate structure extending in a second direction parallel to the upper surface of the substrate and crossing the first direction;
channels spaced apart from each other in a third direction perpendicular to the upper surface of the substrate, each of the channels extending through the gate structure;
a source/drain layer on a portion of the active pattern adjacent the gate structure, the source/drain layer contacting the channels; and
a sacrificial pattern on an upper surface of each of opposite edges of the portion of the active pattern in the second direction, the sacrificial pattern contacting a lower portion of a sidewall of the source/drain layer and including silicon-germanium.

2. The semiconductor device as claimed in claim 1 , wherein the sacrificial pattern extends in the first direction to contact a lower portion of a corresponding one of opposite sidewalls of the source/drain layer in the second direction.

3. The semiconductor device as claimed in claim 1 , wherein the portion of the active pattern adjacent the gate structure includes a protrusion protruding upwardly in the third direction at each of opposite edges in the second direction, the sacrificial pattern being on the protrusion.

4. The semiconductor device as claimed in claim 1 , further comprising a first fin spacer structure on each of opposite edges of the portion of the active pattern in the second direction, the first fin spacer structure contacting an outer sidewall of the sacrificial pattern.

5. The semiconductor device as claimed in claim 4 , wherein the first fin spacer structure contacts a portion of the active pattern and a portion of the source/drain layer.

6. The semiconductor device as claimed in claim 4 , wherein the first fin spacer structure includes first and second fin spacers sequentially stacked.

7. The semiconductor device as claimed in claim 6 , wherein each of the first and second fin spacers includes a nitride.

8. The semiconductor device as claimed in claim 1 , wherein:
the source/drain layer includes lower and upper portions sequentially stacked in the third direction to be connected with each other, and
a cross-section in the second direction of the lower portion of the source/drain layer has a “U” shape, and a cross-section in the second direction of the upper portion of the source/drain layer has a shape of an ellipse.

9. The semiconductor device as claimed in claim 1 , further comprising a first gate spacer structure covering each of opposite sidewalls of the gate structure in the first direction.

10. The semiconductor device as claimed in claim 9 , wherein the first gate spacer structure includes first and second gate spacers sequentially stacked in the first direction from each of opposite sidewalls of the gate structure, the first gate spacer having a cross-section in the first direction having an “L” shape.

11. The semiconductor device as claimed in claim 10 , wherein each of the first and second gate spacers includes a nitride.

12. The semiconductor device as claimed in claim 1 , wherein each of the channels includes silicon, and the source/drain layer includes silicon doped with n-type impurities or silicon carbide doped with n-type impurities.

13. The semiconductor device as claimed in claim 1 , further comprising an inner spacer between the channels, the inner spacer contacting the source/drain layer and the gate structure.

14. The semiconductor device as claimed in claim 13 , wherein the inner spacer includes a nitride.

15. The semiconductor device as claimed in claim 1 , further comprising:
a third fin spacer on each of opposite edges in the second direction of the portion of the active pattern, the third fin spacer contacting an outer sidewall of the sacrificial pattern; and
a fourth fin spacer covering the third fin spacer and the source/drain layer.

16. A semiconductor device, comprising:
a substrate including a first region and a second region;
first channels on the first region of the substrate, the first channels being spaced apart from each other in a vertical direction perpendicular to an upper surface of the substrate;
second channels on the second region of the substrate, the second channels being spaced apart from each other in the vertical direction;
a first gate structure on the first region of the substrate, the first gate structure covering at least a portion of a surface of each of the first channels;
a second gate structure on the second region of the substrate, the second gate structure covering at least a portion of a surface of each of the second channels;
a first source/drain layer on the first region of the substrate, the first source/drain layer contacting the first channels;
a second source/drain layer on the second region of the substrate, the second source/drain layer contacting the second channels; and
a sacrificial pattern contacting a lower portion of a sidewall of the second source/drain layer, the sacrificial pattern including silicon-germanium,
wherein a lower surface of the first source/drain layer is a convex curved surface in the vertical direction, and a central portion of a lower surface of the second source/drain layer is flat and edges of the lower surface of the second source/drain layer are rounded.

17. The semiconductor device as claimed in claim 16 , wherein a bottom surface of the sacrificial pattern is higher than the lower surface of the second source/drain layer.

18. The semiconductor device as claimed in claim 16 , wherein a cross-section of an upper portion of the first source/drain layer in a direction has a shape of a portion of a pentagon or rectangle, and a cross-section of an upper portion of the second source/drain layer in the direction has a shape of an ellipse.

19. The semiconductor device as claimed in claim 16 , further comprising:
a first fin spacer contacting a lower portion of each of opposite sidewalls of the first source/drain layer in the direction; and
a fin spacer structure contacting an outer sidewall of the sacrificial pattern and a lower portion of each of opposite sidewalls of the second source/drain layer in the direction, the fin spacer structure having a thickness greater than that of the first fin spacer.

20. A semiconductor device, comprising:
an active pattern on a substrate, the active pattern extending in a first direction parallel to an upper surface of the substrate;
a gate structure on the active pattern, the gate structure extending in a second direction parallel to the upper surface of the substrate and crossing the first direction;
channels spaced apart from each other in a third direction perpendicular to the upper surface of the substrate, each of the channels extending through the gate structure in the first direction;
a source/drain layer on a portion of the active pattern at each of opposite sides of the gate structure in the first direction, the source/drain layer contacting the channels; and
a sacrificial pattern and a fin spacer structure sequentially stacked in the second direction on a lower portion of each of opposite sidewalls of the source/drain layer in the second direction, the sacrificial pattern and the fin spacer structure including different materials from each other, and the fin spacer structure directly contacting both the active pattern and a portion

Assignees

• Samsung Electronics Co Ltd

Inventors

• Jeong Soojin
• Kim Sunwook
• Park Junbeom
• Song Seungmin

Classifications

• H10D30/797

  being in source or drain regions, e.g. SiGe source or drain · CPC title

• H10D30/794

  comprising conductive materials, e.g. silicided source, drain or gate electrodes · CPC title

• H10D30/025

  of vertical IGFETs (of VDMOS H10D30/0291; of vertical TFTs H10D30/0318) · CPC title

• H10D84/0144

  Manufacturing their gate insulating layers · CPC title

• H10D84/0147

  Manufacturing their gate sidewall spacers · CPC title