Vertical emitters with integrated final-stage transistor switch

Patent metadata

Field	Value
Publication number	US-12494618-B2
Application number	US-202217944213-A
Country	US
Kind code	B2
Filing date	Sep 14, 2022
Priority date	Sep 14, 2022
Publication date	Dec 9, 2025
Grant date	Dec 9, 2025

Abstract

An integrated emitter device incudes a silicon die, including an array of control circuits, and a plurality of integrated emitter modules disposed on the silicon die. Each integrated emitter module includes a single epitaxial stack comprising multiple layers of III-V semiconductor compounds, which define a vertical emitter including an optically active layer and upper and lower distributed Bragg reflectors (DBRs) on opposing sides of the optically active layer, and a transistor in series with the vertical emitter and including a terminal in contact with a respective one of the control circuits, so as to actuate the vertical emitter in response to a control signal applied to the terminal by the respective one of the control circuits.

First claim

The invention claimed is:

1 . An integrated emitter device, comprising:
a silicon die, comprising an array of control circuits; and a plurality of integrated emitter modules disposed on the silicon die, each integrated emitter module comprising a single epitaxial stack comprising multiple layers of III-V semiconductor compounds, which define:
a vertical emitter comprising an optically active layer and upper and lower distributed Bragg reflectors (DBRs) on opposing sides of the optically active layer; and
a transistor in series with the vertical emitter and comprising a terminal in contact with a respective one of the control circuits, so as to actuate the vertical emitter in response to a control signal applied to the terminal by the respective one of the control circuits,
wherein the transistor comprises a base, a collector, and an emitter, wherein the base and the collector are disposed over the upper DBR, outside a cavity of the vertical emitter, while the emitter of the transistor is disposed between the optically active layer and one or more of the layers of the upper DBR.

2 . The device according to claim 1 , wherein the transistor comprises a heterojunction bipolar transistor (HBT).

3 . The device according to claim 1 , wherein the transistor comprises a bipolar junction transistor (BJT).

4 . The device according to claim 1 , wherein the optically active layer comprises quantum wells.

5 . The device according to claim 1 , wherein the vertical emitter is configured as a vertical-cavity surface-emitting laser (VCSEL).

6 . The device according to claim 1 , wherein the vertical emitter in each of the integrated emitter modules comprises a III-V semiconductor substrate, wherein the lower DBR is disposed on the substrate, the optically active layer is disposed over the lower DBR, and the upper DBR is disposed over the optically active layer, and wherein the vertical emitter is configured to emit optical radiation through the III-V semiconductor substrate when the control signal is applied to the terminal of the transistor.

7 . The device according to claim 6 , wherein the terminal of the transistor is bonded to a contact on the silicon die, whereby the vertical emitter emits the optical radiation through the III-V semiconductor substrate in a direction away from the silicon die.

8 . A method for manufacturing, comprising:
fabricating an array of control circuits on a silicon die; fabricating a plurality of integrated emitter modules, each integrated emitter module comprising a single epitaxial stack comprising multiple layers of III-V semiconductor compounds, which define:
a vertical emitter comprising an optically active layer and upper and lower distributed Bragg reflectors (DBRs) on opposing sides of the optically active layer; and
a transistor in series with the vertical emitter and comprising a terminal,
wherein the transistor comprises a base, a collector, and an emitter, wherein the base and the collector are disposed over the upper DBR, outside a cavity of the vertical emitter, while the emitter of the transistor is disposed between the optically active layer and one or more of the layers of the upper DBR; and
bonding the terminal of the transistor in each of the integrated emitter modules to a respective one of the control circuits, whereby the vertical emitter is actuated in response to a control signal applied to the terminal by the respective one of the control circuits.

9 . The method according to claim 8 , wherein the transistor comprises a heterojunction bipolar transistor (HBT).

10 . The method according to claim 8 , wherein the transistor comprises a bipolar junction transistor (BJT).

11 . The method according to claim 8 , wherein the optically active layer comprises quantum wells.

12 . The method according to claim 8 , wherein the vertical emitter is configured as a vertical-cavity surface-emitting laser (VCSEL).

13 . The method according to claim 8 , wherein fabricating the plurality of integrated emitter modules comprises depositing the lower DBR on a III-V semiconductor substrate, depositing the optically active layer over the lower DBR, and depositing the upper DBR over the optically active layer, wherein the vertical emitter is configured to emit optical radiation through the III-V semiconductor substrate when the control signal is applied to the terminal of the transistor.

14 . The method according to claim 13 , wherein bonding the terminal comprises bonding the terminal of the transistor to a contact on the silicon die, whereby the vertical emitter emits the optical radiation through the III-V semiconductor substrate in a direction away from the silicon die.

Assignees

• Apple Inc

Inventors

• Joshi Siddharth
• Lyon Keith
• Laflaquière Arnaud
• Verove Christophe

Classifications

• H01S5/423 Primary

  having a vertical cavity · CPC title

• H01S5/042

  Electrical excitation {; Circuits therefor (monolithically integrated laser drive components H01S5/0261)} · CPC title

• H01S5/0239

  Combinations of electrical or optical elements · CPC title

• H01S5/04257

  having positive and negative electrodes on the same side of the substrate · CPC title

• H01S5/0234

  Up-side down mountings, e.g. Flip-chip, epi-side down mountings or junction down mountings · CPC title