Vertical cavity surface emitting laser array and method for manufacturing the same

Patent metadata

Field	Value
Publication number	US-9865994-B2
Application number	US-201615002607-A
Country	US
Kind code	B2
Filing date	Jan 21, 2016
Priority date	Jul 22, 2013
Publication date	Jan 9, 2018
Grant date	Jan 9, 2018

Abstract

A VCSEL array includes a base substrate, a plurality of VCSEL devices and an inter-device line. Each of the plurality of VCSEL devices is disposed on a front side of the base substrate. The inter-device line connects two of the plurality of VCSEL devices that are adjacent to each other, the two VCSEL devices being connected in series such that forward directions of the two VCSEL devices are the same. An insulating groove that electrically insulates the two VCSEL devices is formed on the base substrate.

First claim

The invention claimed is:

1. A vertical cavity surface emitting laser array comprising:
a semi-insulating semiconductor substrate;
a plurality of vertical cavity surface emitting laser devices formed on a front side of the semi-insulating semiconductor substrate; and
an inter-device line that connects n (n is a natural number≧2) of the plurality of vertical cavity surface emitting laser devices that are adjacent to each other, the n vertical cavity surface emitting laser devices being connected in series such that forward directions of the n vertical cavity surface emitting laser devices are the same,
wherein an insulating region that electrically insulates the n vertical cavity surface emitting laser devices is formed on the semi-insulating semiconductor substrate
when a resistance value of the insulating region formed between two adjacent VCSEL devices is expressed by R ISO , a following formula is satisfied,
I LEAK =( Vf×n )/ R ISO <If× 0.1%,

wherein I LEAK is a leak current, Vf is a value of a load voltage applied to each of the vertical cavity surface emitting laser devices connected in series, and If is a load current.

2. The vertical cavity surface emitting laser array according to claim 1 ,
wherein the insulating region is an insulating groove that is shaped so as to be recessed into the semi-insulating semiconductor substrate from the front side of the semi-insulating semiconductor substrate.

3. The vertical cavity surface emitting laser array according to claim 2 , wherein an insulation protection film is formed on a front surface of the insulating groove.

4. The vertical cavity surface emitting laser array according to claim 3 , wherein the insulation protection film is a film made of silicon nitride.

5. The vertical cavity surface emitting laser array according to claim 2 , wherein the insulating groove has a forward tapered shape such that a cross sectional area of the insulating groove decreases along a direction from the front side to a back side of the semi-insulating semiconductor substrate.

6. The vertical cavity surface emitting laser array according to claim 1 ,
wherein the insulating region is a high resistance region formed to divide a layer that is provided on the semi-insulating semiconductor substrate and on which the n vertical cavity surface emitting laser devices are formed, the high resistance region having an electrical resistivity higher than an electrical resistivity of the semi-insulating semiconductor substrate.

7. The vertical cavity surface emitting laser array according to claim 1 ,
wherein each of the plurality of vertical cavity surface emitting laser devices includes
an active region, and
a first-conductivity-type semiconductor multilayer-film reflective layer and a second-conductivity-type semiconductor multilayer-film reflective layer that sandwich the active region,
wherein the second-conductivity-type semiconductor multilayer-film reflective layer is provided between the first-conductivity-type semiconductor multilayer-film reflective layer and the semi-insulating semiconductor substrate,
wherein the semi-insulating semiconductor substrate includes a first-conductivity-type conductive semiconductor layer formed so as to extend from the front surface toward a back side of the semi-insulating semiconductor substrate, and
wherein the insulating region is an insulating groove that is shaped so as to be recessed into the first-conductivity-type conductive semiconductor layer from the front side of the semi-insulating semiconductor substrate.

8. The vertical cavity surface emitting laser array according to claim 1 ,
wherein each of the plurality of vertical cavity surface emitting laser devices includes
an active region, and
a first-conductivity-type semiconductor multilayer-film reflective layer and a second-conductivity-type semiconductor multilayer-film reflective layer that sandwich the active region,
wherein the second-conductivity-type semiconductor multilayer-film reflective layer is provided between the first-conductivity-type semiconductor multilayer-film reflective layer and the semi-insulating semiconductor substrate,
wherein the semi-insulating semiconductor substrate includes a first-conductivity-type conductive semiconductor layer formed so as to extend from the front surface toward a back side of the semi-insulating semiconductor substrate, and
wherein the insulating region includes a high resistance region formed to divide the first-conductivity-type conductive semiconductor layer, the high resistance region having an electrical resistivity higher than an electrical resistivity of the first-conductivity-type conductive semiconductor layer.

9. A method for manufacturing a vertical cavity surface emitting laser array, comprising:
forming a plurality of vertical cavity surface emitting laser devices on a front side of a semi-insulating semiconductor substrate;
forming an insulating region between n (n is a natural number≧2) of the plurality of vertical cavity surface emitting laser devices that are adjacent to each other, the insulating region electrically insulating the n vertical cavity surface emitting laser devices; and
forming an inter-device line after the step of forming the insulating region, the inter-device line connecting the n vertical cavity surface emitting laser devices in series such that forward directions of the n vertical cavity surface emitting laser devices are the same
when a resistance value of the insulating region formed between two adjacent VCSEL devices is expressed by R ISO , a following formula is satisfied,
I LEAK =( Vf×n )/ R ISO <If× 0.1%,

wherein I LEAK is a leak current, Vf is a value of a load voltage applied to each of the vertical cavity surface emitting laser devices connected in series, and If is a load current.

10. The method for manufacturing a vertical cavity surface emitting laser array according to claim 9 ,
wherein the forming of the insulating region includes forming an insulating groove that is shaped so as to be recessed into the semi-insulating semiconductor substrate from the front side of the semi-insulating semiconductor substrate.

11. The method for manufacturing a vertical cavity surface emitting laser array according to claim 9 ,
wherein the forming of the insulating region includes forming a high resistance region by ion implantation to divide a layer that is provided on the semi-insulating semiconductor substrate and on which the n vertical cavity surface emitting laser devices are formed, the high resistance region having an electrical resistivity higher than an electrical resistivity of the semi-insulating semiconductor substrate.

12. The method for manufacturing a vertical cavity surface emitting laser array according to claim 10 , further comprising:
performing a burn-in test in which a load current is supplied to the n vertical cavity surface emitting laser devices through the inter-device line; and
removing the inter-device line after the step of performing the burn-in test.

13. The method for manufacturing a vertical cavity surface emitting laser array according to claim 10 ,
wherein each of the plurality of vertical cavity surface emitting laser devices includes
an anode electrode and a cathode electrode,
an anode electrode pad and a cathode electrode pad formed for wire bonding,
an anode wire that electrically connects the anode electrode and the anode electrode pad, and
a cathode wire that electrically connects the cathode electrode and the cathode electrode pad, and
wherein the forming the inter-device line includes forming the anode electrode pad, the cathode electro

Assignees

• Murata Manufacturing Co

Inventors

• Matsubara Ippei
• Kona Takayuki
• Iwata Keiji

Classifications

• H01S5/04257

  having positive and negative electrodes on the same side of the substrate · CPC title

• H01S5/04256

  characterised by the configuration · CPC title

• H10W70/60

  Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) · CPC title

• H01S5/4018

  Lasers electrically in series · CPC title

• H01S5/423 Primary

  having a vertical cavity · CPC title