Tunable optical phase filter

Patent metadata

Field	Value
Publication number	US-2017005455-A1
Application number	US-201514956888-A
Country	US
Kind code	A1
Filing date	Dec 2, 2015
Priority date	Jul 2, 2015
Publication date	Jan 5, 2017
Grant date	—

Abstract

An embodiment provides a 850 nm VCSEL transmitter that includes an active region having: one or more quantum wells having InGaAs material; and two or more quantum well barriers having AlGaAs or GaAsP materials adjacent to the one or more quantum wells. An in-phase or anti-phase, step or ring surface relief structure depth control is made on either (i) the topmost GaAs surface/contact layers by either dry or wet etching, or (ii) with the help of PECVD made thin SiN layer made on GaAs layer with wet etching for tunable static and dynamic characteristics such as output power, slope efficiency, and resonance oscillation bandwidth, photon lifetime through its damping, rise/fall times of eye-opening, over shooting, and jitter respectively. Moreover, anti-phase surface relief structure diameter control can be made on the topmost GaAs step surface/contact, or SiN ring layers for filtering of higher order modes and reduction of spectral line width.

First claim

What is claimed is:

1 . A vertical cavity surface-emitting laser element (VCSEL), comprising:
a top distributed Bragg reflector (DBR) and a bottom DBR each made with multiple layers of semiconductor thin films; an active region having at least one quantum well and at least one quantum well barrier each having a thickness of 3-10 nm formed between the top DBR and the bottom DBR, the at least one quantum well comprising InGaAs with an In composition of 0.04-0.12, the at least one quantum well barrier comprising Al x GaAs where x is between 0.3-0.4 or GaAsP y where y is between 0.2-0.3, wherein the at least one quantum well is adjusted for a photoluminescence emission target between 835-840 nm; and a surface relief structure formed on at least the top-most layer of the top DBR by dry or wet etching of semiconductor or dielectric thin films, wherein the surface relief structure has a depth of 20-150 nm and a diameter of 2-6 um, and the top surface of the top-most layer is terminated (1) either in-phase or anti-phase in relation to a standing wave corresponding to the VCSEL, and/or (2) in a layer having a fixed thickness in between the anti-phase and in-phase condition of the standing wave.

2 . A vertical cavity surface-emitting laser element (VCSEL), comprising:
a top distributed Bragg reflector (DBR) and a bottom DBR each made with multiple layers of semiconductor thin films; an active region having at least one quantum well and at least one quantum well barrier each having a thickness of 3-10 nm formed between the top DBR and the bottom DBR, the at least one quantum well comprising InGaAs with an In composition of 0.04-0.12, the at least one quantum well barrier comprising Al x GaAs where x is between 0.3-0.4 or GaAsP y where y is between 0.2-0.3, wherein the at least one quantum well is adjusted for a photoluminescence emission target between 835-840 nm; and a semiconductor step or ring surface relief structure having a depth of 20-50 nm and a diameter of 2-6 um formed on at least one top most layers of the top DBR, the top most layer being p-doped, and wherein the top-most layer is terminated (1) either in-phase or anti-phase in relation to a standing wave corresponding the VCSEL, and/or (2) in a layer having a fixed thickness in between the anti-phase and in-phase condition of the standing wave.

3 . A vertical cavity surface-emitting laser element (VCSEL), comprising:
a top distributed Bragg reflector (DBR) and a bottom DBR each made with multiple layers of semiconductor thin films; an active region having at least one quantum well and at least one quantum well barrier each having a thickness of 3-10 nm formed between the top DBR and the bottom DBR, the at least one quantum well comprising InGaAs with an In proportion of 0.04-0.12, the at least one quantum well barrier comprising Al x GaAs where x is between 0.3-0.4 or GaAsP y where y is between 0.2-0.3, wherein the at least one quantum well is adjusted for a photoluminescence emission target between 835-840 nm; and a dielectric step or ring surface relief structure having a depth of 20-150 nm and a diameter of 2-6 um formed on at least one top-most layer of the top DBR, the top-most layer being p-doped, wherein the surface relief structure is formed by wet chemical etching of dielectric layers fabricated on the at least one top-most layer, and wherein the top-most dielectric layer is terminated (1) either in-phase or anti-phase in relation to a standing wave corresponding the VCSEL, and/or (2) in a layer having a fixed thickness in between the anti-phase and in-phase condition of the standing wave.

4 : The VCSEL according to claim 1 , 2 , or 3 , wherein the emission wavelength is in the wavelength range of 850-860 nm.

5 . The VCSEL according to claim 4 , wherein the VCSEL includes both anode and cathode electrical contacts arranged as top-top configuration.

6 . The VCSEL according to claim 4 , wherein the VCSEL is grown on p-doped or n-doped or un-doped (semi-insulating) GaAs substrate.

7 . The VCSEL according to claim 4 , further comprising at least one Al x Ga 1-x As oxidation layer with Al content of at least 98 percent, and when multiple oxide layers are available, forming at least one oxide layer placed above and below optical cavity/gain region of the VCSEL.

8 . The VCSEL according to claim 4 , further comprising mesa passivation with low dielectric constant (∈) materials, (preferably ∈<3.0).

9 . The VCSEL according to claim 8 , wherein the low dielectric constant materials include one or more of SiN and BCB.

10 . The VCSEL according to claim 2 or 3 , wherein the emission wavelength is in the range of 850-860 nm, and wherein the diameter of the surface relief structure in anti-phase top surface termination is configured in relation to a diameter of an oxide aperture to filter lateral optical modes.

11 . A VCSEL according to claim 1 , wherein the surface relief structure is formed on the top-most layer and one or more layers consecutively below the top-most layer, wherein the layers in which the surface relief is formed includes one or more of P ++ GaAs contact, AlGaAs GIRN, or Al 0.12 GaAs layers.

12 . A VCSEL according to claim 1 , wherein the dry etching includes inductively coupled plasma reactive ion etching (ICP-RIE).

13 . A VCSEL according to claim 3 , wherein the dielectric layer comprises SiN.

14 . A method of manufacturing a vertical cavity surface-emitting laser element (VCSEL), comprising:
forming a top distributed Bragg reflector (DBR), a bottom DBR and an active region, wherein the top and bottom DBRs each being with multiple layers of semiconductor thin films, and wherein the active region having at least one quantum well and at least one quantum well barrier each having a thickness of 3-10 nm formed between the top DBR and the bottom DBR, the at least one quantum well comprising InGaAs with an In proportion of 0.04-0.12, the at least one quantum well barrier comprising Al x GaAs where x is between 0.3-0.4 or GaAsP y where y is between 0.2-0.3, wherein the at least one quantum well is adjusted for a photoluminescence emission target between 835-840 nm; and forming a surface relief structure formed on at least the top-most layer of the top DBR by dry or wet etching of semiconductor or dielectric thin films, wherein the surface relief structure has a depth of 20-150 nm and a diameter of 2-6 um, and the top surface of the top-most layer is terminated (1) either in-phase or anti-phase in relation to a standing wave corresponding the VCSEL, and/or (2) in a layer having a fixed thickness in between the anti-phase and in-phase condition of the standing wave.

15 . A method of manufacturing a vertical cavity surface-emitting laser element (VCSEL), comprising:
forming a top distributed Bragg reflector (DBR), a bottom DBR and an active region, wherein the top and bottom DBRs each being with multiple layers of semiconductor thin films, and wherein the active region having at least one quantum well and at least one quantum well barrier each having a thickness of 3-10 nm formed between the top DBR and the bottom DBR, the at least one quantum well comprising InGaAs with an In proportion of 0.04-0.12, the at least one quantum well barrier comprising Al x GaAs where x is between 0.3-0.4 or GaAsP y where y is between 0.2-0.3, wherein the at least one quantum well is adjusted for a photoluminescence emission target between 835-840 nm; and forming a semiconductor step or ring surface relief structure having a depth of 20-50 nm and a diameter of 2-6 um formed on at least one top most layers of the top DBR, the top most layer being p

Assignees

• Sae Magnetics Hk Ltd

Inventors

• Padullaparthi Babu Dayal

Classifications

• H01S5/3434

  with a well layer comprising at least both As and P as V-compounds · CPC title

• H01S5/0425

  Electrodes, e.g. characterised by the structure · CPC title

• H01S5/34313

  with a well layer having only As as V-compound, e.g. AlGaAs, InGaAs · CPC title

• H01S5/18313

  by oxidizing at least one of the DBR layers · CPC title

• H01S5/18361 Primary

  Structure of the reflectors, e.g. hybrid mirrors · CPC title