Vertical cavity surface emitting laser array

Patent metadata

Field	Value
Publication number	US-9692211-B2
Application number	US-201615002682-A
Country	US
Kind code	B2
Filing date	Jan 21, 2016
Priority date	Jul 22, 2013
Publication date	Jun 27, 2017
Grant date	Jun 27, 2017

Abstract

A VCSEL array includes a base substrate, VCSEL element columns arranged in a row direction (y direction) on a front-surface side of the base substrate and parallel wiring lines that connect the VCSEL element columns in parallel with each other. Each of the VCSEL element columns includes a plurality of VCSEL elements arranged in a column direction (x direction) and a plurality of series wiring lines. The plurality of series wiring lines serially connect every two VCSEL elements that are adjacent to each other in the column direction among the plurality of VCSEL elements in such an orientation that the forward directions of the two VCSEL elements match. Insulating grooves are formed on the base substrate. The insulating grooves electrically insulate the VCSEL element columns from each other. The insulating grooves electrically insulate the VCSEL elements from each other.

First claim

The invention claimed is:

1. A vertical cavity surface emitting laser array comprising:
a semiconductor substrate;
a plurality of vertical cavity surface emitting laser element columns arranged in a row direction on a front-surface side of the semiconductor substrate; and
parallel wiring lines that connect the plurality of vertical cavity surface emitting laser element columns in parallel with each other;
wherein the plurality of vertical cavity surface emitting laser element columns each include
a plurality of vertical cavity surface emitting laser elements arranged in a column direction, and
a plurality of series wiring lines that serially connect every two of the vertical cavity surface emitting laser elements that are adjacent to each other in the column direction among the plurality of vertical cavity surface emitting laser elements in such an orientation that forward directions of the two vertical cavity surface emitting laser elements match, and
a first insulating region that electrically insulates the plurality of vertical cavity surface emitting laser element columns from each other and a second insulating region that electrically insulates the plurality of vertical cavity surface emitting laser elements from each other are formed in the semiconductor substrate.

2. The vertical cavity surface emitting laser array according to claim 1 , further comprising:
at least one pair of dummy pads that are electrically connected to the parallel wiring lines in order to supply a load current from burn-in test probes to the plurality of vertical cavity surface emitting laser element columns.

3. The vertical cavity surface emitting laser array according to claim 2 ,
wherein the plurality of vertical cavity surface emitting laser elements are arranged inside a quadrangular region on the front-surface side of the semiconductor substrate, and
the pair of dummy pads are arranged near a first corner and a second corner positioned on a diagonal line among first to fourth corners corresponding to the four corners of the quadrangular region.

4. The vertical cavity surface emitting laser array according to claim 3 ,
wherein the parallel wiring lines each include a plurality of wiring line portions that each connect in parallel two vertical cavity surface emitting laser element columns that are adjacent to each other in the row direction, and
a resistance value of each of the plurality of wiring line portions is set so as to be inversely proportional to a value of the load current that will flow through the wiring line portion in a state where the load current is supplied to the plurality of vertical cavity surface emitting laser element columns.

5. The vertical cavity surface emitting laser array according to claim 4 ,
wherein each of the plurality of wiring line portions is configured so as to have a wiring line width that corresponds to a value of the load current that will flow through the wiring line portion in a state where the load current is supplied to the plurality of vertical cavity surface emitting laser element columns.

6. The vertical cavity surface emitting laser array according to claim 2 ,
wherein the plurality of vertical cavity surface emitting laser element columns includes
a first vertical cavity surface emitting laser element column including m vertical cavity surface emitting laser elements, where m is a natural number of 2 or more, and
a second vertical cavity surface emitting laser element column including n vertical cavity surface emitting laser elements, where n is a natural number that is smaller than m, and

at least one of the pair of dummy pads is arranged in a region corresponding to the area of m−n vertical cavity surface emitting laser elements in the vicinity of the second vertical cavity surface emitting laser element column on the front-surface side of the semiconductor substrate.

7. The vertical cavity surface emitting laser array according to claim 6 ,
wherein the second vertical cavity surface emitting laser element column further includes a dummy element that causes a voltage drop to be generated that corresponds to the size of a voltage drop that would be caused by the m−n vertical cavity surface emitting laser elements.

8. The vertical cavity surface emitting laser array according to claim 1 ,
wherein the plurality of vertical cavity surface emitting laser elements each has
an anode electrode and a cathode electrode,
an anode electrode pad electrically connected to the anode electrode, and
a cathode electrode pad electrically connected to the cathode electrode,

the parallel wiring lines each include
a plurality of wiring line portions that each connect in parallel two vertical cavity surface emitting laser element columns that are adjacent to each other in the row direction, and

the plurality of wiring line portions are each arranged between one cathode electrode pad and another cathode electrode pad of two vertical cavity surface emitting laser elements that are adjacent to each other in the row direction.

9. The vertical cavity surface emitting laser array according to claim 1 ,
wherein the semiconductor substrate has a semi-insulating property,
the first and second insulating regions are each an insulating groove having a shape that is recessed from the front-side surface of the semiconductor substrate toward the inside of the semiconductor substrate, and
the parallel wiring lines each include a wiring line portion formed on the insulating groove of the second insulating region.

10. The vertical cavity surface emitting laser array according to claim 1 ,
wherein the semiconductor substrate has a semi-insulating property and the first and second insulating regions are each a high-resistance region that has a higher electrical resistivity than the semiconductor substrate.

Assignees

• Murata Manufacturing Co

Inventors

• Matsubara Ippei
• Kona Takayuki
• Iwata Keiji

Classifications

• H10W70/60

  Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) · CPC title

• H01L2224/24

  Electricity · mapped topic

• H01S5/4018

  Lasers electrically in series · CPC title

• H01S5/042

  Electrical excitation {; Circuits therefor (monolithically integrated laser drive components H01S5/0261)} · CPC title

• H01S5/02276

  Electricity · mapped topic