Semiconductor memory device having bit lines with different height

Patent metadata

Field	Value
Publication number	US-12489054-B2
Application number	US-202218047704-A
Country	US
Kind code	B2
Filing date	Oct 19, 2022
Priority date	Mar 21, 2022
Publication date	Dec 2, 2025
Grant date	Dec 2, 2025

Abstract

A semiconductor memory device may include a device isolation pattern in a substrate and defining a first active section of the substrate and a second active section of the substrate, a first bit line crossing the center of the first active section, a second bit line crossing a center of the second active section, a bit-line contact between the first bit line and a center of the first active section, and a storage node pad on an end of the second active section. The first and second active sections may be spaced apart from each other. The center of the first active section may be adjacent to the end of the second active section. A level of a bottom surface of the first bit line may be lower than a level of a bottom surface of the second bit line.

First claim

What is claimed is:

1 . A semiconductor memory device, comprising:
a substrate; a device isolation pattern in the substrate, the device isolation pattern defining a first active section of the substrate and a second active section of the substrate that are spaced apart from each other, a center of the first active section being adjacent to an end of the second active section; a first bit line crossing the center of the first active section; a second bit line crossing a center of the second active section; a bit-line contact between the first bit line and the center of the first active section; and a storage node pad on the end of the second active section, wherein a level of a bottom surface of the first bit line is lower than a level of a bottom surface of the second bit line.

2 . The semiconductor memory device of claim 1 , wherein
the first bit line includes a first diffusion barrier pattern and a first bit-line wire pattern that are sequentially stacked, and the second bit line includes a second diffusion barrier pattern and a second bit-line wire pattern that are sequentially stacked.

3 . The semiconductor memory device of claim 2 , wherein a level of a bottom surface of the first diffusion barrier pattern is lower than a level of a bottom surface of the second diffusion barrier pattern.

4 . The semiconductor memory device of claim 2 , wherein a thickness of the first diffusion barrier pattern is equal to a thickness of the second diffusion barrier pattern.

5 . The semiconductor memory device of claim 2 , wherein
the first diffusion barrier pattern and the second diffusion barrier pattern include a first metallic material, and the first bit-line wire pattern and the second bit-line wire pattern include a second metallic material.

6 . The semiconductor memory device of claim 2 , further comprising:
an interlayer dielectric layer between the substrate and the second bit line, wherein the first diffusion barrier pattern is in contact with the bit-line contact, and wherein the second diffusion barrier pattern is in contact with the interlayer dielectric layer.

7 . The semiconductor memory device of claim 6 , wherein
the interlayer dielectric layer includes a first interlayer dielectric layer and a second interlayer dielectric layer that are sequentially stacked, the first interlayer dielectric layer includes silicon oxide, the second interlayer dielectric layer includes silicon nitride, and the second diffusion barrier pattern is in contact with the second interlayer dielectric layer.

8 . The semiconductor memory device of claim 6 , further comprising:
a first bit-line polysilicon pattern between the first diffusion barrier pattern and the bit-line contact; and a second bit-line polysilicon pattern between the second diffusion barrier pattern and the interlayer dielectric layer.

9 . The semiconductor memory device of claim 1 , further comprising:
a storage node contact between the first bit line and the second bit line, the storage node contact being adjacent to the storage node pad; and an ohmic layer between the storage node contact and the storage node pad, wherein a bottom surface of the ohmic layer is rounded.

10 . The semiconductor memory device of claim 1 , further comprising:
a pad isolation pattern, wherein the bit-line contact is on one side of the storage node pad, the pad isolation pattern is on an other side of the storage node pad, and a bottom end of the pad isolation pattern is below a bottom end of the storage node pad.

11 . A semiconductor memory device, comprising:
a substrate; a device isolation pattern in the substrate, the device isolation pattern defining a first active section of the substrate and a second active section of the substrate that are spaced apart from each other, a center of the first active section being adjacent to an end of the second active section; a first bit line crossing the center of the first active section; a second bit line crossing a center of the second active section; a bit-line contact between the first bit line and the center of the first active section; and a storage node pad on the end of the second active section, wherein a height of the first bit line from a top surface of the substrate is different from a height of the second bit line from the top surface of the substrate.

12 . The semiconductor memory device of claim 11 , wherein the first bit line is below the second bit line.

13 . The semiconductor memory device of claim 11 , wherein
the first bit line includes a first diffusion barrier pattern and a first bit-line wire pattern that are sequentially stacked, and the second bit line includes a second diffusion barrier pattern and a second bit-line wire pattern that are sequentially stacked, the first diffusion barrier pattern and the second diffusion barrier pattern include at least one of titanium, titanium nitride (TiN), titanium silicon nitride (TiSiN), tantalum, tantalum nitride, and tungsten nitride, and the first bit-line wire pattern and the second bit-line wire pattern include at least one of tungsten, aluminum, copper, ruthenium, and iridium.

14 . The semiconductor memory device of claim 13 , further comprising:
an interlayer dielectric layer between the substrate and the second bit line; a first bit-line polysilicon pattern between the first diffusion barrier pattern and the bit-line contact; and a second bit-line polysilicon pattern between the second diffusion barrier pattern and the interlayer dielectric layer.

15 . The semiconductor memory device of claim 11 , wherein the first bit line and the second bit line have a same length along a direction perpendicular to the top surface of the substrate.

16 . The semiconductor memory device of claim 11 , further comprising:
a pad isolation pattern, wherein the bit-line contact is on one side of the storage node pad, the pad isolation pattern is on an other side of the storage node pad, and a top surface of the pad isolation pattern and a top surface of the storage node pad are coplanar with each other.

17 . The semiconductor memory device of claim 16 , wherein the second bit line vertically overlaps the pad isolation pattern.

18 . A semiconductor memory device, comprising:
a substrate including a cell array region and an interface region; a device isolation pattern on the cell array region, the device isolation pattern defining a first active section of the substrate, a second active section of the substrate, and a third active section of the substrate, the first active section, the second active section, and the third active section being spaced apart from each other, a center of the first active section being adjacent to an end of the second active section, and the third active section being adjacent to the interface region; a first bit line crossing the center of the first active section; a second bit line crossing a center of the second active section; a third bit line crossing a center of the third active section; a bit-line contact between the first bit line and the center of the first active section; a first storage node pad on the end of the second active section; and a second storage node pad on an end of the third active section, wherein a thickness of the second storage node pad is greater than a thickness of the first storage node pad, and wherein a level of a bottom surface of the first bit line is lower than a level of a bottom surface of the second bit line.

19 . The semiconductor me

Assignees

• Samsung Electronics Co Ltd

Inventors

• Ahn Junhyeok
• Lee Myeong-Dong

Classifications

• H10W20/4451

  Semiconductor materials, e.g. polysilicon · CPC title

• H10W20/47

  comprising two or more dielectric layers having different properties, e.g. different dielectric constants · CPC title

• H10W10/17

  formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10W10/014 Primary

  using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10W20/435 Primary

  Cross-sectional shapes or dispositions of interconnections · CPC title