Semiconductor devices including capacitors and methods of manufacturing the same

Patent metadata

Field	Value
Publication number	US-10879248-B2
Application number	US-201916281487-A
Country	US
Kind code	B2
Filing date	Feb 21, 2019
Priority date	Dec 24, 2015
Publication date	Dec 29, 2020
Grant date	Dec 29, 2020

Abstract

A semiconductor device includes a substrate, a conductive pattern on the substrate, a lower electrode electrically connected to the conductive pattern, a dielectric layer covering a surface of the lower electrode, a first upper electrode on the dielectric layer, a diffusion barrier on an upper surface of the first upper electrode, and a second upper electrode covering the diffusion barrier, the second upper electrode including a different material from that of the first upper electrode.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a gate structure buried in a substrate, the gate structure including a gate insulation pattern, a gate electrode and a gate mask sequentially stacked, the gate insulation pattern covering a bottom and a sidewall of the gate electrode, and the gate mask being on top surfaces of the gate electrode and the gate insulation pattern;
first and second source/drain regions at upper portions, respectively, of the substrate adjacent to the gate structure;
a bit line on the first source/drain region;
a conductive contact on the second source/drain region; and
a capacitor electrically connected to the conductive contact, the capacitor including:
a lower electrode;
a dielectric layer on the lower electrode;
a first upper electrode on the dielectric layer, the first upper electrode including:
pillars having facing sidewalls in direct contact with each other, and
seams between tops of adjacent ones of the pillars;

a diffusion barrier on the first upper electrode, the diffusion barrier having a plurality of pieces spaced apart from each other, each of the plurality of pieces having a curved top surface and filling a respective one of the seams; and
a second upper electrode on the diffusion barrier.

2. The semiconductor device as claimed in claim 1 , wherein each of the pillars of the first upper electrode has a rounded upper surface, the rounded upper surface facing the second upper electrode, and the seams of the first upper electrode being at contact points between rounded upper surfaces of adjacent ones of the pillars.

3. The semiconductor device as claimed in claim 2 , wherein at least a portion of the rounded upper surface of each of the pillars is not covered by the diffusion barrier.

4. The semiconductor device as claimed in claim 1 , wherein the diffusion barrier includes a conductive metal oxide or a conductive metal oxynitride.

5. The semiconductor device as claimed in claim 4 , wherein the diffusion barrier includes titanium oxide or titanium oxynitride.

6. The semiconductor device as claimed in claim 1 , wherein the first upper electrode includes a metal or a metal nitride, and the second upper electrode includes a silicon-based compound.

7. The semiconductor device as claimed in claim 6 , wherein the second upper electrode includes at least one of doped polysilicon, doped amorphous silicon, silicon-germanium (SiGe), or doped SiGe.

8. The semiconductor device as claimed in claim 6 , wherein the first upper electrode includes titanium nitride.

9. The semiconductor device as claimed in claim 1 , wherein the dielectric layer includes a plurality of layers, and at least one layer of the plurality of layers includes a metal oxide.

10. The semiconductor device as claimed in claim 9 , wherein the dielectric layer includes at least one of zirconium oxide, hafnium oxide, or aluminum oxide.

11. The semiconductor device as claimed in claim 10 , wherein the dielectric layer has a triple-layered structure, and each layer of the triple-layered structure includes at least one of zirconium oxide, hafnium oxide, or aluminum oxide.

12. A semiconductor device, comprising:
a gate structure extending through a substrate;
first and second source/drain regions at upper portions, respectively, of the substrate adjacent to the gate structure;
a bit line on the first source/drain region, the bit line including a conductive pattern structure and a mask pattern sequentially stacked, the conductive pattern structure including a plurality of conductive patterns;
a conductive contact on the second source/drain region; and
a capacitor electrically connected to the conductive contact, the capacitor including:
a lower electrode;
a dielectric layer on the lower electrode;
a first upper electrode on the dielectric layer, the first upper electrode having a rounded upper surface;
a diffusion barrier on the first upper electrode, the diffusion barrier discontinuously covering the rounded upper surface of the first upper electrode; and
a second upper electrode on the diffusion barrier.

13. The semiconductor device as claimed in claim 12 , wherein:
the first upper electrode includes:
pillars having facing sidewalls in direct contact with each other, and
seams between tops of adjacent ones of the pillars and defining the rounded upper surface of the first upper electrode, the diffusion barrier at least partially filling the seams, and

a distance from an uppermost surface of the dielectric layer to an uppermost surface of the diffusion barrier in each of the seams is smaller than a distance from the uppermost surface of dielectric layer to an uppermost surface of each of the pillars, the first upper electrode extending above the diffusion barrier.

14. The semiconductor device as claimed in claim 13 , wherein each of the pillars of the first upper electrode has a rounded surface.

15. The semiconductor device as claimed in claim 14 , wherein at least a portion of the rounded surface of each of the pillars is not covered by the diffusion barrier.

16. The semiconductor device as claimed in claim 12 , wherein the first upper electrode includes a metal or a metal nitride, the diffusion barrier includes a conductive metal oxide or a conductive metal oxynitride, and the second upper electrode includes doped or undoped silicon, or doped or undoped silicon-germanium (SiGe).

17. The semiconductor device as claimed in claim 12 , wherein the conductive pattern structure includes a first conductive pattern, a barrier conductive pattern, and a second conductive pattern sequentially stacked.

18. A semiconductor device, comprising:
an active pattern on a substrate, a sidewall of the active pattern being at least partially covered by an isolation layer;
a gate structure extending through the active pattern and the isolation layer;
first and second impurity regions at upper portions, respectively, of the active pattern adjacent to the gate structure, sidewalls of the first and second impurity regions not being covered by the isolation layer;
a bit line electrically connected to the first impurity region;
a conductive contact electrically connected to the second impurity region; and
a capacitor electrically connected to the conductive contact, the capacitor including:
a lower electrode;
a dielectric layer on the lower electrode;
a first upper electrode on the dielectric layer, the first upper electrode including:
pillars having facing sidewalls in direct contact with each other, and
seams between tops of adjacent ones of the pillars;

a diffusion barrier on the first upper electrode, the diffusion barrier having a plurality of pieces spaced apart from each other, each of the plurality of pieces having a curved top surface and filling a respective one of the seams; and
a second upper electrode on the diffusion barrier.

19. The semiconductor device as claimed in claim 18 , wherein:
each of the pillars of the first upper electrode has a rounded upper surface, the seams of the first upper electrode being between rounded upper surfaces of adjacent ones of the pillars, and
at least a portion of the rounded upper surface of each of the pillars is not covered by the diffusion barrier, the second upper electrode being conformal on the first upper electrode and the diffusion barrier.

20. The semiconductor device as claimed in claim 18 , wherein the first upper electrode includes a metal or a metal nitride, the diffusion barrier includes a conductive metal oxide or a conduc

Assignees

• Samsung Electronics Co Ltd

Inventors

• Choi Hoon-Sang
• JEONG Hyeok-Jin
• Lim Jung-Kun
• Tak Young-Mo
• Han Sung-Kil

Classifications

• H10P14/6322

  Formation by thermal treatments (formation by plasma treatment H10P14/6319) · CPC title

• H10P14/6304

  Formation by oxidation, e.g. oxidation of the substrate · CPC title

• H10D1/716

  having vertical extensions · CPC title

• H10D1/696

  comprising multiple layers, e.g. comprising a barrier layer and a metal layer (barrier layers to prevent diffusion of hydrogen or oxygen in perovskite based capacitors H10D1/688) · CPC title

• H10D1/042 Primary

  using deposition processes to form electrode extensions · CPC title