Method of manufacturing integrated circuit device

Patent metadata

Field	Value
Publication number	US-9953985-B2
Application number	US-201715629523-A
Country	US
Kind code	B2
Filing date	Jun 21, 2017
Priority date	Jul 6, 2016
Publication date	Apr 24, 2018
Grant date	Apr 24, 2018

Abstract

A method of manufacturing an integrated circuit device includes forming multilayered stack structures that extend parallel to and separated from one another on a substrate, followed by forming a buried conductive layer including a plurality of conductive line patterns that extend parallel to an extending direction of the multilayered stack structures and alternate with the multilayered stack structures; removing portions of the buried conductive layer to thereby separate the plurality of conductive line patterns of the buried conductive layer from one another as a plurality of contact plugs and, at the same time, form a plurality of insulating fence spaces that alternate with the plurality of contact plugs in the extending direction of the multilayered stack structures; and forming a plurality of insulating fences that fill the plurality of insulating fence spaces and include a plurality of insulating line patterns extending parallel to one another.

First claim

What is claimed is:

1. A method of manufacturing an integrated circuit device, the method comprising:
forming a plurality of multilayered stack structures that extend parallel to and separated from one another on a substrate;
forming a buried conductive layer including a plurality of conductive line patterns that extend parallel to an extending direction of the multilayered stack structures, each of the plurality of conductive line patterns being between each of the multilayered stack structures;
removing portions of the buried conductive layer that correspond to a plurality of fence line areas which are spaced apart from one another and extend parallel to one another in a direction crossing the extending direction of the multilayered stack structures, to thereby separate the plurality of line patterns of the buried conductive layer from one another as a plurality of contact plugs and, at the same time, form a plurality of insulating fence spaces that alternate with the plurality of contact plugs in the extending direction of the multilayered stack structures; and
forming a plurality of insulating fences that include a plurality of insulating line patterns filling the plurality of insulating fence spaces and extending parallel to one another along the plurality of fence line areas.

2. The method as claimed in claim 1 , wherein each of the multilayered stack structures includes a conductive line, a capping layer covering the conductive line, and insulating spacers covering opposite sidewalls of the conductive line and opposite sidewalls of the capping layer, and
forming the buried conductive layer includes filling spaces defined between the multilayered stack structures by the insulating spacers.

3. The method as claimed in claim 1 , further comprising, before forming the buried conductive layer:
exposing portions of the substrate between the multilayered stack structures;
etching the exposed portions of the substrate between the multilayered stack structures to form a plurality of first recess spaces in the substrate, the plurality of first recess spaces having a first substrate depth from an upper surface of the substrate; and
forming the buried conductive layer includes filling the plurality of first recess spaces.

4. The method as claimed in claim 1 , further comprising:
forming a plurality of word lines that are buried in the substrate, and a plurality of buried insulating layers covering the plurality of word lines, before forming the multilayered stack structures; and before forming the buried conductive layer, exposing portions of the substrate and portions of the plurality of buried insulating layers between the multilayered structure stacks, and etching the exposed portions of the substrate and the exposed portions of the plurality of buried insulating layers, which are exposed between the multilayered structures, to form a plurality of first recess spaces in the substrate and the buried insulating layers, the first recess spaces in the substrate having a first substrate depth from an upper surface of the substrate, the first recess spaces in the buried insulating layers having a first insulation depth from the upper surfaces of the buried insulating layers, and
wherein forming the buried conductive layer includes filling the plurality of first recess spaces.

5. The method as claimed in claim 4 , wherein forming the plurality of insulating fence spaces includes:
exposing portions of the plurality of buried insulating layers in the plurality of first recess spaces by removing portions of the buried conductive layer that correspond to the plurality of fence line areas; and
forming a plurality of second recess spaces by etching the exposed portions of the plurality of buried insulating layers, the plurality of second recess spaces having a second insulation depth from the upper surfaces of the plurality of buried insulating layers, the second insulating depth being greater than the first insulation depth.

6. The method as claimed in claim 4 , wherein forming the plurality insulating fence spaces includes reducing heights of portions of the multilayered stack structures in the plurality of fence line areas while removing portions of the buried conductive layer that correspond to the plurality of fence line areas to thereby form repeating step patterns in the upper surfaces of the plurality of multilayered stack structures, along a lengthwise direction of the multilayered stack structures.

7. The method as claimed in claim 1 , wherein forming the plurality of insulating fences includes:
forming insulating line portions and a plurality of insulating plug portions, the insulating line portions extending on the multilayered stack structures in a direction intersecting the multilayered stack structures, the plurality of insulating plug portions extending from the insulating line portions toward the substrate to fill the plurality of insulating fence spaces, the plurality of insulating plugs portions being integrally connected with a corresponding one of the insulating line portions.

8. The method as claimed in claim 1 , wherein forming the plurality of insulating fences includes:
forming an insulating layer having a thickness sufficient to fill the plurality of insulating fence spaces;
planarizing the insulating layer so that the plurality of contact plugs are exposed, to thereby form insulating line portions of which upper surfaces extend on the same plane as the upper surfaces of the plurality of contact plugs, and a plurality of insulating plug portions that extending from the insulating line portions toward the substrate to fill the plurality of insulating fence spaces, the plurality of insulating plug portions being integrally connected with a corresponding one of the insulating line portions.

9. A method of manufacturing an integrated circuit device, the method comprising:
forming a plurality of first conductive lines in a substrate to extend parallel to one another in a first direction;
forming a plurality of second conductive lines on the substrate to extend parallel to one another in a second direction that intersects the first direction;
forming a buried conductive layer including a plurality of conductive line patterns that extend on the substrate parallel to the second direction, each of the plurality of conductive line patterns being interposed between each of the plurality of second conductive lines;
removing portions of the buried conductive layer that vertically overlap with the plurality of first conductive lines, to thereby separate the plurality of conductive line patterns of the buried conductive layer from one another as a plurality of contact plugs and, at the same time, form a plurality of insulating fence spaces that alternate with the plurality of contact plugs in the second direction: and
forming a plurality of insulating fences that include a plurality of insulating line patterns filling the plurality of insulating fence spaces, vertically overlapping with the plurality of first conductive lines, and extending parallel to one another.

10. The method as claimed in claim 9 , wherein:
forming the buried conductive layer includes forming the buried conductive layer so that portions of the buried conductive layer that vertically overlap with the plurality of first conductive lines have bottom surfaces separated by a first distance from the plurality of first conductive lines, and
forming the plurality of insulating fences includes forming the plurality of insulating fences so that portions of the plurality of insulating fences that vertically overlap with the plurality of first conductive lines have bottom surfaces separated by a second distance from the plurality of first condu

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Hyun-Gi
• Jeong Sang-Moo
• Kim Seon-Ju
• Kim Hye-Won

Classifications

• H10P95/06

  Planarisation of inorganic insulating materials · CPC title

• H10P50/642

  Chemical etching · CPC title

• H10P50/283

  by chemical means · CPC title

• H10P50/264

  by chemical means · CPC title

• H10P50/71

  using masks for conductive or resistive materials · CPC title