Semiconductor device including air gaps and method of fabricating the same

Patent metadata

Field	Value
Publication number	US-9627253-B2
Application number	US-201615142885-A
Country	US
Kind code	B2
Filing date	Apr 29, 2016
Priority date	Jan 19, 2015
Publication date	Apr 18, 2017
Grant date	Apr 18, 2017

Abstract

A semiconductor device including air gaps and a method of fabricating the same. The semiconductor device in accordance with an embodiment may include a bit line structure having a bit line formed over a first contact plug, a second contact plug formed adjacent to the first contact plug and the bit line structure, an air gap structure comprising two or more air gaps to surround the second contact plug and have an outer sidewall in contact with the bit line structure, and one or more capping support layers separating the air gaps, a third contact plug capping a part of the air gap structure and being formed over the second contact plug, and a capping layer for capping a remainder of the air gap structure.

First claim

What is claimed is:

1. A method of fabricating semiconductor device, comprising:
forming a first interlayer dielectric layer comprising a first open part over a substrate;
forming a first contact plug to fill the first open part and forming a bit line structure comprising a bit line over the first contact plug;
forming a second interlayer dielectric layer over a resultant structure including the bit line structure;
forming a second open part of a hole-shaped structure which has sidewalls provided by the second interlayer dielectric layer and the bit line structure, by etching the second interlayer dielectric layer;
sequentially forming a first sacrificial spacer, a capping support layer, and a second sacrificial spacer over the sidewalls of the second open part;
forming a second contact plug to partially fill the second open part;
forming a first air gap surrounding the second contact plug by removing the second sacrificial spacer;
forming a third interlayer dielectric layer over a resultant structure including the second contact plug;
forming a third open part to partially expose the second contact plug and the first sacrificial spacer by etching the third interlayer dielectric layer;
forming a second air gap surrounding the second contact plug by removing the first sacrificial spacer; and
forming a third contact plug to fill the third open part.

2. The method of claim 1 , wherein the forming of the first contact plug and the bit line structure comprises:
forming a preliminary-first contact plug to fill the first open part;
forming the bit line structure comprising the bit line over the preliminary-first contact plug; and
forming the first contact plug spaced apart from sidewalls of the first open part with a gap by etching the preliminary-first contact plug.

3. The method of claim 2 , further comprising:
forming plug spacers to fill the gap.

4. The method of claim 3 , wherein a top surface of each of the plug spacers is positioned at a level equal to or lower than a top surface of the first contact plug.

5. The method of claim 1 , wherein the forming of the second interlayer dielectric layer comprises:
forming an interlayer dielectric layer over a surface of a resultant structure including the bit line structure; and
performing a planarization process on the interlayer dielectric layer until a top surface of the bit line structure is exposed.

6. The method of claim 1 , wherein a width of the first sacrificial spacer is equal to or greater than a width of the second sacrificial spacer.

7. The method of claim 1 , wherein:
the first sacrificial spacer and the capping support layer each comprise an insulating substance, and
the second sacrificial spacer comprises a metal-containing substance.

8. The method of claim 1 , wherein the first sacrificial spacer, the capping support layer, and the second sacrificial spacer have a ring-shaped structure.

9. The method of claim 1 , further comprising:
extending a bottom part of the second open part by etching the first interlayer dielectric layer under the second open part before forming the second contact plug.

10. The method of claim 1 , further comprising:
forming a temporary capping layer over the first air gap before forming the third interlayer dielectric layer.

11. The method of claim 10 , wherein the temporary capping layer and the first sacrificial spacer are formed by the same substance.

12. The method of claim 1 , further comprising:
forming a memory element coupled to the third contact plug.

13. The method of claim 1 , further comprising:
forming a buried word line in the substrate before forming the first interlayer dielectric layer.

14. The method of claim 13 , wherein the forming of the second open part comprises:
forming a mask pattern overlapping with the buried word line over the second interlayer dielectric layer; and
etching the second interlayer dielectric layer using the mask pattern.

Assignees

• Sk Hynix Inc

Inventors

• Kim Min-Ho

Classifications

• H10W20/495

  Capacitive arrangements or effects of, or between wiring layers · CPC title

• H10W20/47

  comprising two or more dielectric layers having different properties, e.g. different dielectric constants · CPC title

• H10W20/089

  using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning · CPC title

• H10W20/083

  the openings being via holes penetrating underlying conductors · CPC title

• H10W20/077

  on sidewalls or on top surfaces of conductors (H10W20/076 takes precedence) · CPC title