Integrated assemblies having bitline contacts, and methods of forming integrated assemblies

Patent metadata

Field	Value
Publication number	US-11056494-B2
Application number	US-201916653658-A
Country	US
Kind code	B2
Filing date	Oct 15, 2019
Priority date	Jun 18, 2018
Publication date	Jul 6, 2021
Grant date	Jul 6, 2021

Abstract

Some embodiments include an integrated assembly having a paired-memory-cell-region within a memory-array-region. The paired-memory-cell-region includes a bitline-contact-structure between a first charge-storage-device-contact-structure and a second charge-storage-device-contact-structure. A first insulative region is between the bitline-contact-structure and the first charge-storage-device-contact-structure. A second insulative region is between the bitline-contact-structure and the second charge-storage-device-contact-structure. The first and second insulative regions both include a first semiconductor material which is in a nonconductive configuration. A transistor gate is over a peripheral region proximate the memory-array-region. The transistor gate has a second semiconductor material which is a same semiconductor composition and thickness as the first semiconductor material, but which is in a conductive configuration. Some embodiments include methods of forming integrated assemblies.

First claim

I claim:

1. A method of forming an integrated assembly, comprising:
providing a construction comprising a memory-array-region having a base-semiconductor-material;
forming trenches extending into the base-semiconductor-material of the memory-array-region; a cross-section along the memory-array-region including a paired-memory-cell-region having two neighboring trenches extending into the base-semiconductor-material; the trenches being a first trench and a second trench; a first pillar of the base-semiconductor-material being on one side of the first trench; a second pillar of the base-semiconductor-material being between the first and second trenches, and being on an opposing side of the first trench from the first pillar of the base-semiconductor-material; a third pillar of the base-semiconductor-material being on an opposing side of the second trench from the second pillar of the base-semiconductor-material; the first and third pillars of the base-semiconductor-material comprising first and second charge-storage-device-contact-locations, respectively; the second pillar of the base-semiconductor-material comprising a bitline-contact-location;
forming a first conductive structure coupled with the bitline-contact-location;
forming second and third conductive structures coupled with the first and second charge-storage-device-contact-locations, respectively; and
forming a first insulative region between the first and second conductive structures, and forming a second insulative region between the second and third conductive structures; the first and second insulative regions both comprising a first semiconductor material which is in a nonconductive configuration.

2. The method of claim 1 comprising coupling the first conductive structure with a bitline, coupling the second conductive structure with a first charge-storage device, and coupling the third conductive structure with a second charge-storage device; a neighboring pair of memory cells comprising the first, second and third pillars of the base-semiconductor-material, together with the first and second charge-storage devices; the neighboring pair of memory cells and sharing a connection to the bitline which extends through the second conductive structure.

3. The method of claim 1 comprising coupling the first conductive structure with a bitline, coupling the second conductive structure with a first capacitor, and coupling the third conductive structure with a second capacitor; a neighboring pair of memory cells comprising the first, second and third pillars of the base-semiconductor-material, together with the first and second capacitors; the neighboring pair of memory cells and sharing a connection to the bitline which extends through the second conductive structure.

4. The method of claim 1 wherein the first and second insulative regions include insulative material in addition to the first semiconductor material.

5. The method of claim 4 wherein the insulative material comprises silicon nitride.

6. The method of claim 1 wherein the construction includes a peripheral region proximate the memory-array-region; the method comprising forming one or more transistor gates over the peripheral region; said one or more transistor gates being formed to have a second semiconductor material which is a same semiconductor composition as the first semiconductor material, and which is a same thickness as the first semiconductor material; the second semiconductor material being conductively-doped.

7. The method of claim 6 wherein said one or more transistor gates are formed to include a third semiconductor material over the second semiconductor material, the third semiconductor material being spaced from the second semiconductor material by an insulative material.

8. The method of claim 7 wherein the insulative material comprises silicon dioxide.

9. The method of claim 7 wherein the third semiconductor material comprises the same semiconductor composition as the first and second semiconductor materials.

10. The method of claim 7 wherein the third semiconductor material comprises a different semiconductor composition relative to the first and second semiconductor materials.

11. A method of forming an integrated assembly, comprising:
providing a construction comprising a memory-array-region, and comprising a peripheral region proximate the memory-array-region; the construction including a base-semiconductor-material within the memory-array-region and within the peripheral region;
forming trenches extending into the base-semiconductor-material of the memory-array-region; a cross-section along the memory-array-region including a paired-memory-cell-region having two neighboring trenches extending into the base-semiconductor-material; the trenches being a first trench and a second trench; a first pillar of the base-semiconductor-material being on one side of the first trench; a second pillar of the base-semiconductor-material being between the first and second trenches, and being on an opposing side of the first trench from the first pillar of the base-semiconductor-material; a third pillar of the base-semiconductor-material being on an opposing side of the second trench from the second pillar of the base-semiconductor-material; the first and third pillars of the base-semiconductor-material comprising first and second charge-storage-device-contact-locations, respectively; the second pillar of the base-semiconductor-material comprising a bitline-contact-location;
forming a first wordline within the first trench, and forming a second wordline within the second trench; the first wordline comprising a first gate along the cross-section, and the second wordline comprising a second gate along the cross-section; the first gate gatedly coupling the bitline-contact-location with the first charge-storage-device-contact-location, and the second gate gatedly coupling the bitline-contact-location with the second charge-storage-device-contact-location;
forming a stack having a first a portion over the memory-array-region and having a second portion over the peripheral region; the stack including an insulative material over a first semiconductor material, and including a second semiconductor material over the insulative material; the first and second semiconductor materials within the stack not being conductively-doped and instead being in a nonconductive configuration;
conductively doping the first and second semiconductor materials of the second portion of the stack while leaving the first and second semiconductor materials of the first portion of the stack in the nonconductive configuration;
removing the second semiconductor material and the insulative material from the first portion of the stack;
incorporating the conductively-doped first semiconductor material, the insulative material and the conductively-doped second semiconductor material into one or more transistor gates associated with the peripheral region;
forming a bitline coupled with the bitline-contact-location; and
forming charge-storage devices coupled with the charge-storage-device-contact-locations.

12. The method of claim 11 wherein the insulative material comprises silicon dioxide.

13. The method of claim 11 wherein the insulative material comprises a thickness within a range of from greater than or equal to about 10 Å to less than or equal to about 100 Å.

14. The method of claim 11 wherein the first and second semiconductor materials comprise the same semiconductor composition as one another.

15. The method of claim 14 wherein the first and second semiconductor materials comprise silicon.

16. The

Assignees

• Micron Technology Inc

Inventors

• Tomoyama Tsuyoshi

Classifications

• H01L27/10894

  Electricity · mapped topic

• H01L27/10823

  Electricity · mapped topic

• H01L27/10888 Primary

  Electricity · mapped topic

• H01L27/10897

  Electricity · mapped topic

• H01L27/10814

  Electricity · mapped topic