Gate-all-around integrated circuit structures having underlying dopant-diffusion blocking layers

Patent metadata

Field	Value
Publication number	US-12484266-B2
Application number	US-202217903914-A
Country	US
Kind code	B2
Filing date	Sep 6, 2022
Priority date	Sep 28, 2018
Publication date	Nov 25, 2025
Grant date	Nov 25, 2025

Abstract

Gate-all-around integrated circuit structures having underlying dopant-diffusion blocking layers are described. For example, an integrated circuit structure includes a vertical arrangement of horizontal nanowires above a fin. The fin includes a dopant diffusion blocking layer on a first semiconductor layer, and a second semiconductor layer on the dopant diffusion blocking layer. A gate stack is around the vertical arrangement of horizontal nanowires. A first epitaxial source or drain structure is at a first end of the vertical arrangement of horizontal nanowires. A second epitaxial source or drain structure is at a second end of the vertical arrangement of horizontal nanowires.

First claim

What is claimed is:

1 . An integrated circuit structure, comprising:
a nanowire above a fin, the fin comprising a layer comprising carbon and silicon; a gate stack around the nanowire, wherein a portion of the gate stack is vertically between the nanowire and the layer comprising carbon and silicon; a first epitaxial source or drain structure at a first end of the nanowire, the first epitaxial source or drain structure having a bottommost surface above a bottommost surface of the layer comprising carbon and silicon; and a second epitaxial source or drain structure at a second end of the nanowire, the second epitaxial source or drain structure having a bottommost surface above the bottommost surface of the layer comprising carbon and silicon.

2 . The integrated circuit structure of claim 1 , wherein the fin comprises a portion of a bulk silicon substrate.

3 . The integrated circuit structure of claim 1 , wherein the first and second epitaxial source or drain structures are on a portion of the layer comprising carbon and silicon.

4 . The integrated circuit structure of claim 1 , wherein the layer comprising carbon and silicon further comprises germanium.

5 . The integrated circuit structure of claim 1 , wherein the layer comprising carbon and silicon further comprises germanium.

6 . The integrated circuit structure of claim 1 , further comprising:
a second nanowire above the nanowire.

7 . The integrated circuit structure of claim 1 , wherein the first and second epitaxial source or drain structures are non-discrete first and second epitaxial source or drain structures.

8 . The integrated circuit structure of claim 1 , wherein the first and second epitaxial source or drain structures are discrete first and second epitaxial source or drain structures.

9 . The integrated circuit structure of claim 1 , wherein the nanowire is a silicon nanowire.

10 . The integrated circuit structure of claim 1 , wherein the nanowire is a silicon germanium nanowire.

11 . The integrated circuit structure of claim 1 , wherein the nanowire is a germanium nanowire.

12 . The integrated circuit structure of claim 1 , wherein the nanowire is a Group III-V material nanowire.

13 . The integrated circuit structure of claim 1 , wherein the gate stack comprises a high-k gate dielectric layer and a metal gate electrode.

14 . The integrated circuit structure of claim 1 , wherein the layer comprising carbon and silicon is a dopant-diffusion blocking layer.

15 . A computing device, comprising:
a board; and a component coupled to the board, the component including an integrated circuit structure, comprising:
a nanowire above a fin, the fin comprising a layer comprising carbon and silicon;
a gate stack around the nanowire, wherein a portion of the gate stack is vertically between the nanowire and the layer comprising carbon and silicon;
a first epitaxial source or drain structure at a first end of the nanowire, the first epitaxial source or drain structure having a bottommost surface above a bottommost surface of the layer comprising carbon and silicon; and
a second epitaxial source or drain structure at a second end of the nanowire, the second epitaxial source or drain structure having a bottommost surface above a bottommost surface of the layer comprising carbon and silicon.

16 . The computing device of claim 15 , further comprising:
a memory coupled to the board.

17 . The computing device of claim 15 , further comprising:
a communication chip coupled to the board.

18 . The computing device of claim 15 , further comprising:
a battery coupled to the board.

19 . The computing device of claim 15 , wherein the component is a packaged integrated circuit die.

20 . The computing device of claim 15 , wherein the component is selected from the group consisting of a processor, a communications chip, and a digital signal processor.

Assignees

• Intel Corp

Inventors

• Glass Glenn
• Murthy Anand
• Guha Biswajeet
• Crum Dax
• Keys Patrick
• Ghani Tahir
• Ghose Susmita
• Cook Jr Ted

Classifications

• H10P76/2043

  using an anti-reflective coating · CPC title

• H10P72/7426

  used as a support during build up manufacturing of active devices · CPC title

• H10P72/744

  Details of chemical or physical process used for separating the auxiliary support from a device or a wafer · CPC title

• H10P72/74

  using temporarily an auxiliary support · CPC title

• H10P52/402

  of semiconductor materials · CPC title