Three-dimensional memory device and method of making thereof by non-conformal selective deposition of insulating spacers in a memory opening

Patent metadata

Field	Value
Publication number	US-12484222-B2
Application number	US-202318355888-A
Country	US
Kind code	B2
Filing date	Jul 20, 2023
Priority date	Jan 11, 2023
Publication date	Nov 25, 2025
Grant date	Nov 25, 2025

Abstract

A method of forming a memory device includes forming an alternating stack of insulating layers including a first insulating material and sacrificial material layers including a first sacrificial material over a substrate, forming a memory opening through the alternating stack, performing a first selective material deposition process that selectively grows a second sacrificial material from physically exposed surfaces of the sacrificial material layers to form a vertical stack of sacrificial material portions; forming a memory opening fill structure in the memory opening, where the memory opening fill structure includes a vertical stack of memory elements and a vertical semiconductor channel, and replacing a combination of the vertical stack of sacrificial material portions and the sacrificial material layers with electrically conductive layers.

First claim

What is claimed is:

1 . A method of forming a memory device, comprising:
forming an alternating stack of insulating layers comprising a first insulating material and sacrificial material layers comprising a first sacrificial material over a substrate; forming a memory opening through the alternating stack; performing a first selective material deposition process that selectively grows a second sacrificial material from physically exposed surfaces of the sacrificial material layers to form a vertical stack of sacrificial material portions; forming a memory opening fill structure in the memory opening, wherein the memory opening fill structure comprises a vertical stack of memory elements and a vertical semiconductor channel; and replacing a combination of the vertical stack of sacrificial material portions and the sacrificial material layers with electrically conductive layers.

2 . The method of claim 1 , wherein the first selective material deposition process comprises a non-conformal depletive atomic layer deposition process in which a thickness of the deposited second sacrificial material decreases with a downward vertical distance from a horizontal plane including a topmost surface of the alternating stack.

3 . The method of claim 1 , wherein:
the first sacrificial material comprise a first silicon nitride material deposited by plasma enhanced chemical vapor deposition; and the second sacrificial material comprises a second silicon nitride material deposited by atomic layer deposition.

4 . The method of claim 1 , further comprising performing a second selective material deposition process that selectively grows a second insulating material from physically exposed surfaces of the insulating layers to form vertical stack of insulating spacers.

5 . The method of claim 4 , wherein:
the second selective material deposition process comprises a non-conformal depletive atomic layer deposition process in which a thickness of the deposited second insulating material decreases with a downward vertical distance from a horizontal plane including a topmost surface of the alternating stack; lateral thicknesses of the insulating spacers of the vertical stack of insulating spacers increases with a vertical distance from a top surface of the substrate; and at least one insulating spacer of the vertical stack of insulating spacers has a middle portion having an inner sidewall and an outer sidewall that are parallel to each other, an upper portion having upper tapered surfaces that are adjoined to each other at an annular top periphery, and a lower portion having lower tapered surfaces that are adjoined to each other at an annular bottom periphery.

6 . The method of claim 1 , wherein the vertical stack of sacrificial material portions has a variable lateral thickness that increases with a lateral distance from a vertical axis passing through a geometrical center of a volume of the memory opening.

7 . The method of claim 1 , wherein each electrically conductive layer within an upper subset of the electrically conductive layers including a topmost electrically conductive layer comprises a respective cylindrical surface that laterally surrounds the memory opening fill structure, an upper tapered annular surface adjoined to an upper periphery of the respective cylindrical surface, and a lower tapered annular surface adjoined to a lower periphery of the respective cylindrical surface.

8 . The method of claim 7 , wherein:
the upper tapered annular surfaces within the upper subset of the electrically conductive layers have different vertical extents that increase in magnitude with a vertical distance from a top surface of the substrate; the cylindrical surfaces within the upper subset of the electrically conductive layers have different vertical extents that decrease in magnitude with a vertical distance from a top surface of the substrate; and each electrically conductive layer within the upper subset of the electrically conductive layers has a same vertical extent between a respective horizontal top surface and a respective horizontal bottom surface.

9 . The method of claim 7 , wherein an electrically conductive layer within the upper subset of the electrically conductive layers comprises:
a horizontally-extending portion having a uniform vertical thickness throughout; and a contoured connection region located between the horizontally-extending region and a combination of the upper tapered annular surface of the electrically conductive layer and the lower tapered annular surface of the electrically conductive layer, wherein a top surface of the contoured connection region has an asymmetric V-shaped vertical cross-sectional profile in which a first top surface segment is longer than a second top surface segment, and a bottom surface of the contoured connection region has an inverted asymmetric V-shaped vertical cross-sectional profile in which a first bottom surface segment is longer than a second bottom surface segment.

10 . The method of claim 7 , wherein:
the memory opening fill structure comprises a layer stack of a blocking dielectric layer, a memory material layer, and a dielectric liner; the vertical stack of memory elements comprises portions of the memory material layer; an outer sidewall of the memory material layer has a lesser taper angle relative to a vertical direction than a taper angle of surface segments of the memory opening fill structure that contact a respective one of the insulating layers relative to the vertical direction; the blocking dielectric layer comprises a vertical stack of annular rib portions at levels of the upper subset of the electrically conductive layers; and two annular rib portions are provided per each electrically conductive layer within the upper subset of the electrically conductive layers.

11 . A memory device, comprising:
an alternating stack of insulating layers and electrically conductive layers located over a substrate; a memory opening vertically extending through the alternating stack; and a memory opening fill structure located in the memory opening and comprising a vertical stack of memory elements and a vertical semiconductor channel, wherein each electrically conductive layer within an upper subset of the electrically conductive layers including a topmost electrically conductive layer comprises a respective cylindrical surface that laterally surrounds the memory opening fill structure, an upper tapered annular surface adjoined to an upper periphery of the respective cylindrical surface, and a lower tapered annular surface adjoined to a lower periphery of the respective cylindrical surface.

12 . The memory device of claim 11 , wherein:
the upper tapered annular surfaces within the upper subset of the electrically conductive layers have different vertical extents that increase in magnitude with a vertical distance from a top surface of the substrate; the cylindrical surfaces within the upper subset of the electrically conductive layers have different vertical extents that decrease in magnitude with a vertical distance from a top surface of the substrate; and each electrically conductive layer within the upper subset of the electrically conductive layers has a same vertical extent between a respective horizontal top surface and a respective horizontal bottom surface.

13 . The memory device of claim 11 , wherein the memory opening fill structure further comprises a vertical stack of insulating spacers that are vertically spaced apart from each other and contacting a respective one of the insulating layers.

14 . The memory device of claim 13 , wherein

Assignees

• Sandisk Technologies Llc
• Sandisk Technologies Inc

Inventors

• Sharangpani Rahul
• Makala Raghuveer S
• RAJASHEKHAR Adarsh
• Zhou Fei
• Zhou Bing
• Kanakamedala Senaka
• Tirukkonda Roshan Jayakhar
• Sondhi Kartik

Classifications

• H10W20/435

  Cross-sectional shapes or dispositions of interconnections · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H10B41/10 Primary

  characterised by the top-view layout · CPC title

• H10B41/35

  with a cell select transistor, e.g. NAND · CPC title

• H10B41/27

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title