Arrangement for a semiconductor arrangement comprising at least one passive component and a substrate

Patent metadata

Field	Value
Publication number	US-12482739-B2
Application number	US-202218834521-A
Country	US
Kind code	B2
Filing date	Nov 28, 2022
Priority date	Feb 1, 2022
Publication date	Nov 25, 2025
Grant date	Nov 25, 2025

Abstract

An arrangement for a semiconductor arrangement includes a substrate including a dielectric material layer and a first metallization arranged on the dielectric material layer. A passive component is arranged completely in a cutout of the first metallization and bears directly on the dielectric material layer. The passive component is designed to include a first profile. The the first metallization includes a second profile in a region of contacting with the passive component, with the first and second profiles engaging with one another.

First claim

The invention claimed is:

1 . A semiconductor arrangement comprising:
a substrate including a dielectric material layer and a first metallization arranged on the dielectric material layer; and a passive component arranged completely in a cutout of the first metallization and bearing directly on the dielectric material layer, said passive component including a first profile having a protrusion and a connection arranged on a side of the protrusion facing away from the dielectric material layer, wherein the first metallization includes a second profile having a recess, with the first profile protrusion and the second profile recess engaging with one another and the connection connecting the passive component to the first metallization.

2 . The arrangement of claim 1 , wherein the passive component is flush with a first surface of the first metallization.

3 . The arrangement of claim 2 , wherein the passive component is connected to the dielectric material layer via a force acting through a form-fit connection perpendicular to the first surface of the first metallization.

4 . The arrangement of claim 1 , wherein the first metallization is embodied as a thick copper substrate, with the passive component being pressed together with the dielectric material layer over an entire surface between two sides of the thick copper substrate.

5 . The arrangement of claim 1 , wherein the passive component is connected directly or via the connection in the cutout of the first metallization.

6 . The arrangement of claim 5 , wherein the passive component is made of a first material, and wherein the connection contains a second material which differs from the first material at least as regards its mechanical and/or thermal properties.

7 . The arrangement of claim 1 , wherein the substrate includes a second metallization which is embodied as a thick copper substrate, with the dielectric material layer being laminated onto the second metallization or pressed together with the second metallization, said second metallization being connected to the first metallization via the dielectric material layer.

8 . The arrangement of claim 1 , wherein the passive component is embodied as a sensor, the arrangement further comprising a terminal for contacting the sensor.

9 . A method for producing an arrangement for a semiconductor arrangement, the method comprising:
providing a passive component with a first profile having a protrusion and a connection arranged on a side of the protrusion facing away from the dielectric material laver; forming a substrate with a dielectric material layer and a first metallization which is arranged on the dielectric material layer and includes a second profile having a recess; arranging the passive component completely in a cutout of the first metallization, such that the passive component bears directly on the dielectric material layer; and engaging the first profile protrusion and the second profile recess with one another and the connection connecting the passive component to the first metallization.

10 . The method of claim 9 , further comprising arranging the passive component in the cutout such as to be flush with a first surface of the first metallization.

11 . The method of claim 9 , wherein the first metallization is embodied as a thick copper substrate, the method further comprising pressing the passive component together with the dielectric material layer over an entire surface between two sides of the thick copper substrate.

12 . The method of claim 9 , further comprising connecting the passive component directly or via connectors in the cutout of the first metallization.

13 . The method of claim 9 , wherein the first metallization is embodied as a thick copper substrate, the method further comprising:
Introducing the passive component into a cavity of the first metallization; connecting the passive component to the first metallization to form a top layer; pressing together the top layer with the dielectric material layer such that the passive component bears directly on the dielectric material layer; arranging a layer of the first metallization on a side facing away from the passive component; and removing the layer, in particular by machining, such that the passive component is exposed and is flush with a first surface of the first metallization.

14 . The method of claim 9 , wherein the first metallization is embodied as a thick copper substrate, the method further comprising:
introducing the passive component into a cavity of the first metallization; connecting the passive component to the first metallization to form a top layer, such that the passive component is flush with a first surface of the first metallization; arranging a layer of the first metallization on a side facing away from the passive component; removing the layer, in particular by machining, such that the passive component is exposed and is flush with a second surface of the first metallization; and pressing together the top layer with the dielectric material layer such that the passive component bears directly on the dielectric material layer.

15 . The method of claim 9 , further comprising:
providing the substrate with a second metallization which is embodied as a thick copper substrate; and laminating the dielectric material layer onto the second metallization or pressing together the dielectric material layer with the second metallization.

Assignees

• Siemens Ag

Inventors

• Lasch Markus
• Lorz Roland
• Pfeifer Markus
• Stegmeier Stefan
• Weisbrod Erik
• Werner Ronny
• Zeyss Felix

Classifications

• H10W90/701

  characterised by the relative positions of pads or connectors relative to package parts · CPC title

• H10W90/401

  characterised by multiple insulating or insulated package substrates, interposers or RDLs · CPC title

• H10W40/255

  having a laminate or multilayered structure, e.g. direct bond copper [DBC] ceramic substrates · CPC title

• H10W70/658 Primary

  for devices provided for in groups H10D8/00 - H10D48/00 · CPC title

• H10W40/00 Primary

  Arrangements for thermal protection or thermal control (integrated devices comprising arrangements for thermal protection H10D89/60) · CPC title