Package substrate

Patent metadata

Field	Value
Publication number	US-2016007486-A1
Application number	US-201514754261-A
Country	US
Kind code	A1
Filing date	Jun 29, 2015
Priority date	Jul 2, 2014
Publication date	Jan 7, 2016
Grant date	—

Abstract

There is provided a package substrate including: a substrate on which a circuit layer and an insulating layer are stacked; a metal post provided in an outside region of at least any one of an upper surface and a lower surface of the substrate; an electronic component mounted in a cavity formed by the metal post; and a metal lid bonded to an upper portion of the metal post.

First claim

What is claimed is:

1 . A package substrate, comprising:
a substrate configured by stacking a circuit layer and an insulating layer; a metal post provided in an outside region of at least any one of an upper surface and a lower surface of the substrate; an electronic component mounted in a cavity formed by the metal post; and a metal lid bonded to an upper portion of the metal post.

2 . The package substrate according to claim 1 , wherein the metal post and the metal lid are made of the same metal material.

3 . The package substrate according to claim 1 , wherein the metal post and the metal lid are made of at least one metal material selected from a group consisting of Kovar, alloy, nickel (Ni), cobalt (Co), and chromium (Cr).

4 . The package substrate according to claim 1 , wherein a height of the metal post is determined depending on a thickness of the electronic component.

5 . The package substrate according to claim 1 , wherein a width of the metal post is determined depending on a size of the electronic component.

6 . The package substrate according to claim 1 , wherein the electronic component is at least any one selected from a group consisting of an RF chip, an IC chip, a capacitor, an inductor, and a resistor.

7 . The package substrate according to claim 1 , further comprising:
a sealing material provided in the cavity to seal the electronic component.

8 . The package substrate according to claim 1 , wherein the metal post is configured of a vertical part and a horizontal part which is bonded to an upper portion of the vertical part and formed to have a larger width than the vertical part.

9 . The package substrate according to claim 1 , further comprising:
a metal layer provided between the metal post and the metal lid.

10 . A method for manufacturing a package substrate, comprising:
forming a substrate configured by stacking a circuit layer and an insulating layer; attaching a resist to at least any one of an upper surface and a lower surface of the substrate; removing an outside portion of the resist; forming a metal post in an outside region of the substrate which is exposed to the outside by removing the outside portion of the resist; delaminating the resist; and mounting an electronic component in a cavity formed by the metal post and bonding a metal lid to an upper portion of the metal post.

11 . The method according to claim 10 , wherein in the removing of the outside portion of the resist, a mask is disposed in the remaining portion except for the outside portion of the resist and then is subjected to an exposure and developing process.

12 . The method according to claim 11 , wherein a size of the mask is changed depending on a size of the electronic component.

13 . The method according to claim 10 , wherein in the forming of the metal post, the outside region of the substrate is plated with a metal material.

14 . The method according to claim 13 , wherein a plated amount of the metal material is controlled depending on a thickness of the electronic component.

15 . The method according to claim 10 , wherein the bonding of the metal lid is performed using at least any one of seam welding, laser welding, and brazing welding.

16 . The method according to claim 10 , wherein prior to the bonding of the metal lid, a sealing material is filled in the cavity to seal the electronic component.

17 . A method for manufacturing a package substrate, comprising:
forming a substrate configured by stacking a circuit layer and an insulating layer; bonding a first resist to at least any one of an upper surface and a lower surface of the substrate; removing an outside portion of the first resist; forming a vertical part of a metal post in an outside region of the substrate which is exposed to the outside by removing the outside portion of the first resist; stacking a second resist on an upper portion of the first resist including the vertical part; removing an outside portion of the second resist at a larger width than a width of the vertical part; forming a horizontal part of the metal post in a region which is exposed to the outside by removing the outside portion of the second resist; delaminating the first and second resists; and mounting an electronic component in a cavity formed by the vertical part and the horizontal part of the metal post and bonding a metal lid to an upper portion of the horizontal part.

Assignees

• Samsung Electro Mech

Inventors

• Kim Yong Suk
• Lee Taek Jung
• Chang Byeung Gyu
• Kim Doo Young
• Lee Byoung Hwa

Classifications

• H10W76/47

  Solid or gel fillings · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W70/685

  comprising multiple insulating layers · CPC title

• H10W70/635

  Through-vias · CPC title

• H10W70/095

  of vias therein · CPC title