Display substrate including shift register and display device

Patent metadata

Field	Value
Publication number	US-12475825-B2
Application number	US-202418637592-A
Country	US
Kind code	B2
Filing date	Apr 17, 2024
Priority date	Oct 28, 2022
Publication date	Nov 18, 2025
Grant date	Nov 18, 2025

Abstract

A display substrate and a display device are provided, the display substrate includes a base substrate, and a shift register and a clock signal line that are on the base substrate; the shift register includes an input circuit, an output circuit, a first control circuit, a second control circuit, a first noise reduction circuit and a second noise reduction circuit; the input circuit includes a first transistor and a second transistor, the first transistor and the second transistor are both oxide transistors, and the second node is connected to the second voltage signal only through the second control circuit, and a potential of the second node is pulled down only through the second control circuit.

First claim

The invention claimed is:

1 . A display substrate, comprising:
a base substrate, wherein a shift register and a clock signal line are on the base substrate; wherein the shift register comprises: an input circuit, an output circuit, a first control circuit, a second control circuit, a first noise reduction circuit and a second noise reduction circuit; an output end of the input circuit, a control end of the output circuit and a control end of the second control circuit are connected to a first node, an input end of the input circuit is connected to a first scanning input end, and an input end of the output circuit is connected to the clock signal line; an output end of the first control circuit, an input end of the second control circuit, a control end of the first noise reduction circuit and a control end of the second noise reduction circuit are connected to a second node, an input end of the first control circuit is configured to be connected with a first voltage signal, and an output end of the first noise reduction circuit and an output end of the second noise reduction circuit are configured to be connected with a second voltage signal; the input circuit comprises a first transistor and a second transistor, a second electrode of the first transistor is connected with a first electrode of the second transistor, a gate electrode of the first transistor is connected with a gate electrode of the second transistor and serves as a control end of the input circuit, a first electrode of the first transistor serves as the input end of the input circuit, and a second electrode of the second transistor serves as the output end of the input circuit, the first transistor and the second transistor are both oxide transistors, and the second node is connected to the second voltage signal only through the second control circuit, and a potential of the second node is pulled down only through the second control circuit; the first control circuit comprises: a seventh transistor, a first electrode of the seventh transistor serves as the input end of the first control circuit, a second electrode of the seventh transistor serves as the output end of the first control circuit, and a gate electrode of the seventh transistor serves as the control end of the first control circuit; the seventh transistor comprises: a first semiconductor block, comprising a first end and a second end; a second semiconductor block, comprising a third end and a fourth end; and a first floating electrode, overlapped with the first semiconductor block and located between the first end and the second end; and a second floating electrode, overlapped with the second semiconductor block and located between the third end and the fourth end, wherein a first electrode of the seventh transistor is connected with the first end and the third end, and a second electrode of the seventh transistor is connected with the second end and the fourth end.

2 . The display substrate according to claim 1 , further comprising: a first voltage line and a second voltage line on the base substrate, wherein the first voltage line is configured to apply the first voltage signal and the second voltage line is configured to apply the second voltage signal;
the second node is connected to the second voltage line only through the second control circuit.

3 . The display substrate according to claim 1 , wherein a channel width-length ratio of the first transistor ranges from 6 to 14, and a channel width-length ratio of the second transistor ranges from 6 to 14.

4 . The display substrate according to claim 1 , wherein the shift register further comprises: a third noise reduction circuit, a control end of the third noise reduction circuit is connected to the second node, an input end of the third noise reduction circuit is connected to the second electrode of the first transistor, and an output end of the third noise reduction circuit is configured to be connected to the second voltage signal;
the third noise reduction circuit is configured to respond to a voltage on the second node to reduce noise for the second electrode of the first transistor by the second voltage signal.

5 . The display substrate according to claim 4 , wherein the third noise reduction circuit comprises: a third transistor, a gate electrode of the third transistor serves as the control end of the third noise reduction circuit, a first electrode of the third transistor serves as the input end of the third noise reduction circuit, and a second electrode of the third transistor serves as the output end of the third noise reduction circuit.

6 . The display substrate according to claim 5 , wherein a channel length of the third transistor is greater than 5 microns.

7 . The display substrate according to claim 1 , wherein the shift register further comprises: a reset circuit, an input end of the reset circuit is connected to the first node, and an output end of the reset circuit is connected to a second scanning input end;
the reset circuit is configured to respond to a reset signal on a control end of the reset circuit to reset the first node through the second scanning input end.

8 . The display substrate according to claim 7 , wherein the reset circuit comprises: a fourth transistor and a fifth transistor, a gate electrode of the fourth transistor is connected with a gate electrode of the fifth transistor and serves as the control end of the reset transistor, a first electrode of the fourth transistor is connected with a second electrode of the fifth transistor, a second electrode of the fourth transistor serves as the output end of the reset circuit, and a first electrode of the fifth transistor serves as the input end of the reset circuit,
the fourth transistor and the fifth transistor are oxide transistors.

9 . The display substrate according to claim 7 , wherein the shift register further comprises: a fourth noise reduction circuit, a control end of the fourth noise reduction circuit is connected to the second node, an input end of the fourth noise reduction circuit is connected to a first electrode of the fourth transistor, and an output end of the fourth noise reduction circuit is configured to be connected to the second voltage signal;
the fourth noise reduction circuit is configured to respond to a voltage on the second node to reduce noise for the first electrode of the fourth transistor by the second voltage signal.

10 . The display substrate according to claim 9 , wherein the fourth noise reduction transistor comprises: a sixth transistor, a gate electrode of the sixth transistor serves as the control end of the fourth noise reduction circuit, a first electrode of the sixth transistor serves as the input end of the fourth noise reduction circuit, and a second electrode of the sixth transistor serves as the output end of the fourth noise reduction circuit.

11 . The display substrate according to claim 10 , wherein a channel length of the sixth transistor is greater than 5 microns.

12 . The display substrate according to claim 1 , wherein the first floating electrode and the second floating electrode are in a continuous integrated structure.

13 . The display substrate according to claim 1 , wherein the second control circuit comprises: an eighth transistor, a gate electrode of the eighth transistor serves as the control end of the second control circuit, a first electrode of the eighth transistor serves as the input end of the second control circuit, and a second electrode of the eighth transistor serves as the output end of the second control circuit.

14 . The display substrate according to claim 1 ,

Assignees

• Chongqing Boe Optoelectronics Tech Co Ltd
• Boe Technology Group Co Ltd
• Beijing Boe Technology Dev Co Ltd

Inventors

• Wang Xiaolin
• Fu Pengcheng
• Min Taeyup
• Dong Zhifu
• Guo Hui

Classifications

• G11C19/28 Primary

  using semiconductor elements (G11C19/14, G11C19/36 take precedence) · CPC title

• G09G2330/04

  Display protection · CPC title

• G09G2320/043

  Preventing or counteracting the effects of ageing · CPC title

• G09G2310/0286

  Details of a shift registers arranged for use in a driving circuit · CPC title

• G09G2310/0267

  Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays · CPC title