Shift register unit, gate line driving device, and driving method

Patent metadata

Field	Value
Publication number	US-10446104-B2
Application number	US-201615518389-A
Country	US
Kind code	B2
Filing date	Sep 30, 2016
Priority date	Oct 8, 2015
Publication date	Oct 15, 2019
Grant date	Oct 15, 2019

Abstract

A shift register unit, a gate line driving device includes multiple stages of the shift register units, and a driving method for being applied to the shift register unit; the shift register unit includes: an input module connected between an input terminal and a pull-up node, and configured to charge the pull-up node; an output module connected between the pull-up node, a first clock signal terminal and an output terminal, and configured to output to the output terminal a first clock signal received at the first clock signal terminal; a pull-up node reset module connected between a reset terminal, a pull-down node and the pull-up node, and configured to reset the pull-up node; and an output reset module connected between a second clock signal terminal, the pull-down node and the output terminal, and configured to reset the output terminal.

First claim

What is claimed is:

1. A shift register unit, comprising:
an input module connected between an input terminal and a pull-up node, and configured to charge the pull-up node when a trigger signal from a previous stage is received at the input terminal;
an output module connected between the pull-up node, a first clock signal terminal and an output terminal, and configured to output to the output terminal a first clock signal received at the first clock signal terminal under control of the pull-up node;
a pull-up node reset module connected between a reset terminal, a pull-down node and the pull-up node, and configured to reset the pull-up node under control of a reset signal inputted at the reset terminal or a level at the pull-down node;
an output reset module connected between a second clock signal terminal, the pull-down node and the output terminal, and configured to reset the output terminal under control of a second clock signal received at the second clock signal terminal or a level at the pull-down node; and
a pull-down node level control module connected between the first clock signal terminal, the second clock signal terminal, the pull-down node and the pull-up node, and configured to control a level at the pull-down node under control of at least one of the first clock signal received at the first clock signal terminal, the second clock signal received at the second clock signal terminal, and a level at the pull-up node,
wherein the pull-down node level control module comprises:
a seventh transistor having a control electrode connected to a first electrode thereof and further connected to the second clock signal terminal;
an eighth transistor having a control electrode connected to the pull-up node, a first electrode connected to a second level input terminal, and a second electrode connected to a second electrode of the seventh transistor;
a ninth transistor having a control electrode connected to the second electrode of the seventh transistor, a first electrode connected to the second clock signal terminal, and a second electrode connected to the pull-down node;
a tenth transistor having a control electrode connected to the pull-up node, a first electrode connected to the pull-down node, and a second electrode connected to the second level input terminal; and
an eleventh transistor having a control electrode connected to the first clock signal terminal, a first electrode connected to the second level input terminal, and a second electrode connected to a gate of the ninth transistor.

2. The shift register unit according to claim 1 , further comprising:
a trigger module connected between the pull-up node and the first clock signal terminal, and configured to provide a trigger signal to a shift register unit in a next stage.

3. The shift register unit according to claim 2 , wherein the trigger module comprises:
a twelfth transistor having a control electrode connected to the pull-up node, a first electrode connected to the first clock signal terminal, and a second electrode connected to a trigger signal output terminal.

4. The shift register unit according to claim 1 , further comprising:
a reset signal output module connected between the pull-up node and the first clock signal terminal, and configured to provide a reset signal to a shift register unit in a previous stage.

5. The shift register unit according to claim 4 , wherein the reset signal output control module comprises:
a thirteenth transistor having a control electrode connected to the pull-up node, a first electrode connected to the first clock signal terminal, and a second electrode connected to the reset signal output terminal.

6. The shift register unit according to claim 1 , further comprising:
an initialization module connected between an initial signal input terminal and the pull-up node, and configured to initialize a level at the pull-up node.

7. The shift register unit according to claim 6 , wherein the initialization module comprises:
a fourteenth transistor having a control electrode connected to the initial signal input terminal, a first electrode connected to the pull-up node, and a second electrode connected to the second level input terminal.

8. The shift register unit according to claim 1 , wherein the input module comprises:
a first transistor having a control electrode connected to the input terminal, a first electrode connected to a first level input terminal, and a second electrode connected to the pull-up node.

9. The shift register unit according to claim 1 , wherein the output module comprises:
a second transistor having a control electrode connected to the pull-up node, a first electrode connected to the first clock signal terminal, and a second electrode connected to the output terminal; and
a capacitor connected in parallel with a gate and a source of the second transistor.

10. The shift register unit according to claim 1 , wherein the pull-up node reset module comprises:
a third transistor having a control electrode connected to the reset terminal, a first electrode connected to the pull-up node, and a second electrode connected to the second level input terminal; and
a fourth transistor having a control electrode connected to the pull-down node, a first electrode connected to the pull-up node, and a second electrode connected to the second level input terminal.

11. The shift register unit according to claim 1 , wherein the output reset module comprises:
a fifth transistor having a control electrode connected to the second clock signal terminal, a first electrode connected to the output terminal, and a second electrode connected to the second level input terminal, and
a sixth transistor having a control electrode connected to the pull-down node, a first electrode connected to the output terminal, and a second electrode connected to the second level input terminal.

12. A gate line driving device, comprising a plurality of the shift register units of claim 1 cascaded in multiple stages, wherein an output terminal of the shift register unit in each stage is connected to one corresponding gate line;
wherein the first clock signal terminal and the second clock signal terminal of the shift register unit in an Nth stage are connected to the first clock signal and the second clock signal, respectively; a trigger signal output terminal of the Nth stage shift register unit is connected to the input terminal of the shift register unit in the (N+2)th stage, a reset signal output terminal of the stage shift register unit in the Nth stage is connected to the reset terminal of the shift register in the (N−3)th stage, and the reset terminal of the shift register unit in the Nth stage is connected to the reset signal output terminal of the shift register unit in the (N+3)th stage;
the first clock signal terminal and the second clock signal terminal of the shift register unit in (N−1)th stage are connected to a third clock signal and a fourth clock signal, respectively;
wherein periods of the first clock signal, the second clock signal, the third clock signal, and the fourth clock signal are the same, a timing of the first clock signal and that of second clock signal are opposite, and the timing of the third clock signal and that of the fourth clock signal are opposite, and the third clock signal lags behind the first clock signal by a quarter of the period.

13. The gate line driving device according to claim 12 , wherein each of the shift register units further comprises:
a trigger module connected between the pull-up node and the first clock signal terminal, and configured to provide a trigger signal to a shift register unit in a next stage.

Assignees

• Boe Technology Group Co Ltd
• Beijing Boe Display Tech Co

Inventors

• Wang Zheng

Classifications

• G11C19/18

  using capacitors as main elements of the stages {(if capacitors are used as auxiliary stage in between main stages with other elements, the latter take precedence; G11C19/005 takes precedence)} · CPC title

• G11C19/287

  Organisation of a multiplicity of shift registers · CPC title

• G09G2310/0283

  Arrangement of drivers for different directions of scanning · CPC title

• G11C19/184

  with field-effect transistors, e.g. MOS-FET · CPC title

• G11C19/28

  using semiconductor elements (G11C19/14, G11C19/36 take precedence) · CPC title