Gate driving circuit on array substrate and liquid crystal display (LCD) using the same

Patent metadata

Field	Value
Publication number	US-10043474-B2
Application number	US-201614916343-A
Country	US
Kind code	B2
Filing date	Feb 24, 2016
Priority date	Jan 7, 2016
Publication date	Aug 7, 2018
Grant date	Aug 7, 2018

Abstract

A gate driving circuit disposed on an array substrate and an LCD using the same are described. The gate driving circuit on the array substrate comprises a plurality of sequentially connected gate driving units. The gate driving circuit unit comprises an input module, a reset module, a latch module and a signal processing module. The signal processing module receives the current inverse stage-transmitting signal XQ(N), the low voltage signal, a second clock signal and a third clock signal to control on/off statuses of two transistors by the current stage-transmitting signal Q(N) so that the two transistors forms Nth gate signal G(N) and gate signal (N+1)th based on the second clock signal and the third clock signal. The present invention utilizes less clock signals and transistors, which is favorable to the narrower LCD's frame design and solves the problem of manufacturing process restriction of the LCD panel.

First claim

What is claimed is:

1. A gate driving circuit which is disposed on an array substrate of a liquid crystal display (LCD), wherein the gate driving circuit on the array substrate comprises a plurality of sequentially connected gate driving units, the gate driving circuit unit comprising:
an input module, for receiving a previous stage-transmitting signal Q(N−1), a previous inverse stage-transmitting signal XQ(N−1) and a low voltage signal to generate a current stage transition signal TP(N) and a current stage-transmitting signal Q(N) wherein the serial number “N” is a positive integer;
a reset module connected to the input module, for receiving a reset signal, a high voltage signal and the low voltage signal to allow the current stage transition signal TP(N) and the current stage-transmitting signal Q(N) to be reset by the reset signal in an initial status, wherein the reset module generates a control signal based on the high voltage signal and the current stage transition signal;
a latch module connected to the reset module, for receiving the control signal, a first clock signal and the high voltage signal, wherein the latch module generates a current inverse stage-transmitting signal XQ(N) according to the control signal and the first clock signal; and
a signal processing module connected to the latch module, for receiving the current inverse stage-transmitting signal XQ(N), the low voltage signal, a second clock signal and a third clock signal to control on/off statuses of two transistors by the current stage-transmitting signal Q(N) so that the two transistors forms Nth gate signal G(N) and gate signal (N+1)th based on the second clock signal and the third clock signal.

2. The gate driving circuit of claim 1 , wherein the input module further comprises:
a first transistor comprising a first source electrode, a first gate electrode and a first drain electrode;
a second transistor comprising a second source electrode, a second gate electrode and a second drain electrode; and
a third transistor comprising a third source electrode, a third gate electrode and a third drain electrode;
wherein the first source electrode is connected to the third source electrode for receiving the current stage-transmitting signal Q(N);
wherein the first drain electrode, the second source electrode and the third drain electrode are connected together for receiving the current stage transition signal TP(N);
wherein the first gate electrode is connected to the second gate electrode for receiving the previous stage-transmitting signal Q(N−1), the third gate electrode receives the previous inverse stage-transmitting signal XQ(N−1), and the second drain electrode receives the low voltage signal.

3. The gate driving circuit of claim 1 , wherein the reset module further comprises:
a fourth transistor comprising a fourth source electrode, a fourth gate electrode and a fourth drain electrode;
a fifth transistor comprising a fifth source electrode, a fifth gate electrode and a fifth drain electrode;
a sixth transistor comprising a sixth source electrode, a sixth gate electrode and a sixth drain electrode;
a seventh transistor comprising a seventh source electrode, a seventh gate electrode and a seventh drain electrode;
a eighth transistor comprising an eighth source electrode, an eighth gate electrode and an eighth drain electrode; and
a ninth transistor comprising a ninth source electrode, a ninth gate electrode and a ninth drain electrode;
wherein the fourth gate electrode is connected to the fifth gate electrode for receiving the reset signal, the sixth and eighth gate electrodes receives the current stage-transmitting signal Q(N), the seventh and ninth gate electrodes receives the current stage transition signal TP(N), the fifth source electrode receives the high voltage signal, and the fourth drain electrode is connected to the sixth drain electrode for receiving the low voltage signal;
wherein the fourth source electrode, the seventh source electrode, the eighth drain electrode and the ninth drain electrode are connected together for outputting the control signal;
wherein the fifth drain electrode, the eight drain electrode and the ninth source electrode are connected together.

4. The gate driving circuit of claim 1 , wherein the latch module further comprises:
a first inverter comprising a first input terminal and a first output terminal for receiving the control signal to form an inverse control signal;
a tenth transistor comprising a tenth source electrode, a tenth gate electrode and a tenth drain electrode;
an eleventh transistor comprising an eleventh source electrode, an eleventh gate electrode and an eleventh drain electrode; and
a twelfth transistor comprising a twelfth source electrode, a twelfth gate electrode and a twelfth drain electrode;
wherein the first input terminal is connected to the tenth gate electrode and the twelfth gate electrode for receiving the control signal and the first output terminal is used to output the inverse control signal to the eleventh gate electrode, and the twelfth transistor receives the first clock signal;
wherein the tenth drain electrode, eleventh drain electrode and the twelfth drain electrode are connected together to generate the current inverse stage-transmitting signal XQ(N) and the twelfth source electrode receives the high voltage signal.

5. The gate driving circuit of claim 4 , wherein at least three stages of sequentially connected gate driving circuits on the array substrate comprises a previous stage gate driving circuit, a current stage gate driving circuit and a next stage gate driving circuit;
wherein the current stage gate driving circuit generates a previous stage-transmitting signal Q(N−1) and a previous inverse stage-transmitting signal XQ(N−1), and the latch module of the next stage gate driving circuit further comprises a second inverter having a second input terminal and a second output terminal;
wherein the second input terminal receives the first clock signal to generate an inverse first clock signal and the second output terminal outputs the inverse first clock signal to the tenth source electrode and the eleventh source electrode.

6. The gate driving circuit of claim 1 , wherein the signal processing module further comprises:
a third inverter comprising a third input terminal and a third output terminal wherein the third input terminal receives the current inverse stage-transmitting signal XQ(N) for generating the current stage-transmitting signal Q(N);
a thirteenth transistor comprising a thirteenth source electrode, a thirteenth gate electrode and a thirteenth drain electrode;
a fourteenth transistor comprising a fourteenth source electrode, a fourteenth gate electrode and a fourteenth drain electrode;
a fifteenth transistor comprising a fifteenth source electrode, a fifteenth gate electrode and a fifteenth drain electrode;
a sixteenth transistor comprising a sixteenth source electrode, a sixteenth gate electrode and a sixteenth drain electrode;
a seventeenth transistor comprising a seventeenth source electrode, a seventeenth gate electrode and a seventeenth drain electrode;
an eighteenth transistor comprising an eighteenth source electrode, an eighteenth gate electrode and an eighteenth drain electrode;
a first set of inverter comprising a plurality of sequentially connected fourth inverter wherein the first set of inverter is connected to the thirteenth transistor, the fifteenth transistor and the seventeenth transistor; and
a second set of inverter comprising a plurality of sequentially connected fifth inverter wherein the second set of inverter is connected to the fourteenth transistor, the sixteenth transistor and the eighteenth transistor;
wherein the third input terminal is connected to the fifteenth ga

Assignees

• Wuhan China Star Optoelectronics Technology Co Ltd

Inventors

• Zhao Mang
• Li Yafeng

Classifications

• G09G2310/0289

  Details of voltage level shifters arranged for use in a driving circuit · CPC title

• G09G3/3677 Primary

  suitable for active matrices only · CPC title

• G09G2310/0286

  Details of a shift registers arranged for use in a driving circuit · CPC title

• G09G2310/0243

  Details of the generation of driving signals · CPC title

• G09G2310/08

  Details of timing specific for flat panels, other than clock recovery · CPC title