Shift register, gate driving circuit and display panel

Patent metadata

Field	Value
Publication number	US-11676524-B2
Application number	US-202117789607-A
Country	US
Kind code	B2
Filing date	Sep 15, 2021
Priority date	Oct 28, 2020
Publication date	Jun 13, 2023
Grant date	Jun 13, 2023

Abstract

The present disclosure provides a shift register, a gate driving circuit and a display panel, and belongs to the field of display technology. The shift register of the present disclosure includes: an input circuit configured to precharge and reset a pull-up node; one pull-down control circuit being electrically connected to one pull-down circuit through a pull-down node; the pull-down control circuit being configured to control a potential at the pull-down node under a first power voltage; each pull-down circuit being configured to pull down the potential at the pull-down node in response to a potential at the pull-up node; an output circuit configured to output a clock signal through a signal output terminal in response to the potential at the pull-up node; one first noise reduction circuit connected to one pull-down node.

First claim

What is claimed is:

1. A shift register, comprising: an input circuit, an output circuit, at least one pull-down control circuit, at least one pull-down circuit, at least one first auxiliary circuit and at least one first noise reduction circuit; wherein,
the input circuit is configured to precharge and reset a pull-up node; the input circuit, the pull-down circuit and the output circuit are connected to the pull-up node as a connection node;
one of the at least one pull-down control circuit is electrically connected to one of the at least one pull-down circuit through one of at least one pull-down node; the at least one pull-down control circuit is configured to control at least one potential at the at least one pull-down node under the control of a first power voltage, respectively;
each of the at least one pull-down circuit is configured to pull down the at least one potential at the at least one pull-down node in response to a potential at the pull-up node;
the output circuit is configured to output a clock signal through a signal output terminal in response to the potential at the pull-up node;
one of the at least one first noise reduction circuit is connected to one of the at least one pull-down node; the at least one first noise reduction circuit is configured to denoise the pull-up node and an output of the signal output terminal by a non-operating level signal in response to the at least one pull-down node; and
one of the at least one first auxiliary circuit is electrically connected to one pull-down node; the at least one first auxiliary circuit is configured to pull down a potential at the pull-down node by a non-operating level signal in a precharge stage in response to an input signal.

2. The shift register of claim 1 , wherein the input circuit comprises a first input sub-circuit and a second input sub-circuit;
the first input sub-circuit is configured to charge the pull-up node by a first voltage in response to a first input signal in a forward scanning, and reset the pull-up node by a second voltage in response to a second input signal in a reverse scanning; and
the second input sub-circuit is configured to reset the pull-up node by the second voltage in response to the second input signal in the forward scanning, and charge the pull-up node by the first voltage in response to the first input signal in the reverse scanning.

3. The shift register of claim 2 , wherein the first input sub-circuit comprises a first transistor; the second input sub-circuit comprises a second transistor;
a first electrode of the first transistor is connected to a first voltage terminal, a second electrode of the first transistor is connected to the pull-up node, and a control electrode of the first transistor is connected to a first input signal terminal; and
a first electrode of the second transistor is connected to a second voltage terminal, a second electrode of the second transistor is connected to the pull-up node, and a control electrode of the second transistor is connected to a second input signal terminal.

4. The shift register of claim 2 , wherein the input circuit further comprises a first anticreep sub-circuit and a second anticreep sub-circuit;
the first anticreep sub-circuit is configured to prevent the first input sub-circuit from leaking electricity to affect the potential at the pull-up node in the forward scanning; and
the second anticreep sub-circuit is configured to prevent the second input sub-circuit from leaking electricity to affect the potential at the pull-up node in the reverse scanning.

5. The shift register of claim 4 , wherein the first anticreep sub-circuit comprises a twelfth transistor; the second anticreep sub-circuit comprises a thirteenth transistor;
a first electrode of the twelfth transistor is connected to the first voltage terminal, a second electrode of the twelfth transistor is connected to the first input sub-circuit, and a control electrode of the twelfth transistor is connected to the first input signal terminal; and
a first electrode of the thirteenth transistor is connected to the second voltage terminal, a second electrode of the thirteenth transistor is connected to the second input sub-circuit, and a control electrode of the thirteenth transistor is connected to the second input signal terminal.

6. The shift register of claim 4 , further comprising at least one second noise reduction circuit and at least one third noise reduction circuit;
one of the at least one second noise reduction circuit is connected to one of the at least one pull-down node and is configured to denoise an output of the first anticreep sub-circuit in response to a potential at the pull-down node; and
one of the at least one third noise reduction circuit is connected to one of the at least one pull-down node and is configured to denoise an output of the second anticreep sub-circuit in response to a potential at the pull-down node.

7. The shift register of claim 6 , wherein the second noise reduction circuit comprises an eighteenth transistor; the third noise reduction circuit comprises a nineteenth transistor;
a first electrode of the eighteenth transistor is connected between the first input sub-circuit and the first anticreep sub-circuit, a second electrode of the eighteenth transistor is connected to a non-operating level terminal, and a control electrode of the eighteenth transistor is connected to a corresponding pull-down node; and
a first electrode of the nineteenth transistor is connected between the second input sub-circuit and the second anticreep sub-circuit, a second electrode of the nineteenth transistor is connected to the non-operating level terminal, and a control electrode of the nineteenth transistor are connected to a corresponding pull-down node.

8. The shift register of claim 2 , wherein each of the at least one first auxiliary circuit comprises a first auxiliary sub-circuit and a second auxiliary sub-circuit;
the first auxiliary sub-circuit is configured to pull down the potential at the pull-down node by the non-operating level signal in response to the first input signal in the forward scanning; and
the second auxiliary sub-circuit is configured to pull down the potential at the pull-down node by the non-operating level signal in response to the first input signal in the reverse scanning.

9. The shift register of claim 8 , wherein the first auxiliary sub-circuit comprises a sixteenth transistor; the second auxiliary sub-circuit comprises a seventeenth transistor;
a first electrode of the sixteenth transistor is connected to a corresponding pull-down node, a second electrode of the sixteenth transistor is connected to the non-operating level terminal, and a control electrode of the sixteenth transistor is connected to a first input signal terminal; and
a first electrode of the seventeenth transistor is connected to a corresponding pull-down node, a second electrode of the seventeenth transistor is connected to the non-operating level terminal, and a control electrode of the seventeenth transistor is connected to a second input signal terminal.

10. The shift register of claim 1 , further comprising a frame reset circuit configured to reset the potential at the pull-up node and the potential at the signal output terminal by the non-operating level signal in response to the reset signal in a blank stage.

11. The shift register of claim 10 , wherein the frame reset circuit comprises a fourth transistor and a seventh transistor;
a first electrode of the fourth transistor is connected to the signal output terminal, a second electrode of the fourth transistor is connected to a non-operating level terminal, and a control electrode of the fourth tra

Assignees

• Hefei Xinsheng Optoelectronics Technology Co Ltd
• Boe Technology Group Co Ltd

Inventors

• Xie Yongxian
• Yang Tong
• Qu Feng
• Lv Fengzhen
• Shao Xianjie
• Ma Rui
• Li Rui

Classifications

• G09G2310/0267

  Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays · CPC title

• G09G3/20 Primary

  for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix {no fixed position being assigned to or needed to be assigned to the individual characters or partial characters} · CPC title

• G11C19/287

  Organisation of a multiplicity of shift registers · CPC title

• G09G2310/0286

  Details of a shift registers arranged for use in a driving circuit · CPC title

• G09G2300/0842

  forming a memory circuit, e.g. a dynamic memory with one capacitor · CPC title