Shift register circuit, gate driving circuit and display apparatus

Patent metadata

Field	Value
Publication number	US-11830398-B2
Application number	US-202017434987-A
Country	US
Kind code	B2
Filing date	Dec 28, 2020
Priority date	Feb 24, 2020
Publication date	Nov 28, 2023
Grant date	Nov 28, 2023

Abstract

A shift register circuit includes a first pull-down control sub-circuit and a first noise reduction sub-circuit. The first pull-down control sub-circuit includes a first transistor and a second transistor, and a ratio of a width-to-length ratio of a channel of the second transistor to a width-to-length ratio of a channel of the first transistor is greater than 5:1. The first pull-down control sub-circuit transmits, in response to a first voltage signal received at a first voltage signal terminal, the first voltage signal to a first pull-down node through the first transistor, and transmits a second voltage signal received at a second voltage signal terminal to the first pull-down node through the second transistor under control of a voltage of a pull-up node. The first noise reduction sub-circuit transmits the second voltage signal to the pull-up node under control of a voltage of the first pull-down node.

First claim

What is claimed is:

1. A shift register circuit, comprising:
a first pull-down control sub-circuit including a first transistor and a second transistor, wherein the first transistor is coupled to a first voltage signal terminal and a first pull-down node, and the second transistor is coupled to a pull-up node, a second voltage signal terminal and the first pull-down node; a ratio of a width-to-length ratio of a channel of the second transistor to a width-to-length ratio of a channel of the first transistor is greater than 5:1; the first pull-down control sub-circuit is configured to: transmit, in response to a first voltage signal received at the first voltage signal terminal, the first voltage signal to the first pull-down node through the first transistor; and transmit a second voltage signal received at the second voltage signal terminal to the first pull-down node through the second transistor under control of a voltage of the pull-up node;
a first noise reduction sub-circuit coupled to the first pull-down node, the second voltage signal terminal and the pull-up node, the first noise reduction sub-circuit being configured to transmit the second voltage signal to the pull-up node under control of a voltage of the first pull-down node;
a second pull-down control sub-circuit including a twelfth transistor and a thirteenth transistor, wherein the twelfth transistor is coupled to a fourth voltage signal terminal and a second pull-down node, and the thirteenth transistor is coupled to the pull-up node, the second voltage signal terminal and the second pull-down node; a width-to-length ratio of a channel of the twelfth transistor is equal to the width-to-length ratio of the channel of the first transistor, and a width-to-length ratio of a channel of the thirteenth transistor is equal to the width-to-length ratio of the channel of the second transistor; the second pull-down control sub-circuit is configured to: transmit, in response to a fourth voltage signal received at the fourth voltage signal terminal, the fourth voltage signal to the second pull-down node through the twelfth transistor; and transmit the second voltage signal received at the second voltage signal terminal to the second pull-down node through the thirteenth transistor under the control of the voltage of the pull-up node; and
a fifth noise reduction sub-circuit coupled to the second pull-down node, the pull-up node and the second voltage signal terminal, the fifth noise reduction sub-circuit being configured to transmit the second voltage signal to the pull-up node under control of a voltage of the second pull-down node.

2. The shift register circuit according to claim 1 , wherein the ratio of the width-to-length ratio of the channel of the second transistor to the width-to-length ratio of the channel of the first transistor is greater than or equal to 8:1.

3. The shift register circuit according to claim 1 , wherein the ratio of the width-to-length ratio of the channel of the second transistor to the width-to-length ratio of the channel of the first transistor is less than or equal to 10:1.

4. The shift register circuit according to claim 1 , wherein a width of the channel of the first transistor is in a range of 50 μm to 200 μm, inclusive, and a length thereof is in a range of 3 μm to 5 μm, inclusive.

5. The shift register circuit according to claim 1 , wherein a width of the channel of the second transistor is in a range of 400 μm to 1500 μm, inclusive, and a length thereof is in a range of 3 μm to 5 μm, inclusive.

6. The shift register circuit according to claim 1 , wherein
a control electrode of the first transistor is coupled to a first pull-down control node, a first electrode of the first transistor is coupled to the first voltage signal terminal, and a second electrode of the first transistor is coupled to the first pull-down node;
a control electrode of the second transistor is coupled to the pull-up node, a first electrode of the second transistor is coupled to the second voltage signal terminal, and a second electrode of the second transistor is coupled to the first pull-down node;
the first pull-down control sub-circuit further includes:
a third transistor, wherein a control electrode and a first electrode of the third transistor are coupled to the first voltage signal terminal, and a second electrode of the third transistor is coupled to the first pull-down control node; and
a fourth transistor, wherein a control electrode of the fourth transistor is coupled to the pull-up node, a first electrode of the fourth transistor is coupled to the second voltage signal terminal, and a second electrode of the fourth transistor is coupled to the first pull-down control node.

7. The shift register circuit according to claim 1 , wherein the first noise reduction sub-circuit includes:
a fifth transistor, wherein a control electrode of the fifth transistor is coupled to the first pull-down node, a first electrode of the fifth transistor is coupled to the second voltage signal terminal, and a second electrode of the fifth transistor is coupled to the pull-up node.

8. The shift register circuit according to claim 1 , further comprising:
a first signal output sub-circuit coupled to the pull-up node, a clock signal terminal and a first signal output terminal, the first signal output sub-circuit being configured to transmit a clock signal received at the clock signal terminal to the first signal output terminal under the control of the voltage of the pull-up node;
a signal input sub-circuit coupled to the pull-up node and a signal input terminal, the signal input sub-circuit being configured to transmit, in response to an input signal received at the signal input terminal, the input signal to the pull-up node;
a second noise reduction sub-circuit coupled to the pull-up node, a reset signal terminal and the second voltage signal terminal, the second noise reduction sub-circuit being configured to transmit the second voltage signal received at the second voltage signal terminal to the pull-up node in response to a reset signal received at the reset signal terminal; and
a third noise reduction sub-circuit coupled to the first pull-down node, a third voltage signal terminal and the first signal output terminal, the third noise reduction sub-circuit being configured to transmit a third voltage signal received at the third voltage signal terminal to the first signal output terminal under the control of the voltage of the first pull-down node.

9. The shift register circuit according to claim 8 , wherein
the first signal output sub-circuit includes:
a sixth transistor, wherein a control electrode of the sixth transistor is coupled to the pull-up node, a first electrode of the sixth transistor is coupled to the clock signal terminal, and a second electrode of the sixth transistor is coupled to the first signal output terminal; and
a storage capacitor, wherein a first electrode of the storage capacitor is coupled to the pull-up node, and a second electrode of the storage capacitor is coupled to the first signal output terminal;
the signal input sub-circuit includes:
a seventh transistor, wherein a control electrode and a first electrode of the seventh transistor are coupled to the signal input terminal, and a second electrode of the seventh transistor is coupled to the pull-up node;
the second noise reduction sub-circuit includes:
an eighth transistor, wherein a control electrode of the eighth transistor is coupled to the reset signal terminal, a first electrode of the eighth transistor is coupled to the second voltage signal terminal, and a second electrode of the eighth transistor is coupled to the pull-up node; and
the third noise reduction sub-circuit includes:
a ninth

Assignees

• Beijing Boe Display Tech Co
• Boe Technology Group Co Ltd

Inventors

• Yan Yan
• Ma Yu
• Chen Weitao
• Cui Xiaopeng

Classifications

• G09G3/20 Primary

  for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix {no fixed position being assigned to or needed to be assigned to the individual characters or partial characters} · CPC title

• G11C19/28 Primary

  using semiconductor elements (G11C19/14, G11C19/36 take precedence) · CPC title

• G09G2300/0408

  Integration of the drivers onto the display substrate · CPC title

• G09G2300/0842

  forming a memory circuit, e.g. a dynamic memory with one capacitor · CPC title

• G09G2310/0267

  Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays · CPC title