Serial-gate transistor and nonvolatile memory device including the same

Patent metadata

Field	Value
Publication number	US-12469563-B2
Application number	US-202318120244-A
Country	US
Kind code	B2
Filing date	Mar 10, 2023
Priority date	Aug 8, 2022
Publication date	Nov 11, 2025
Grant date	Nov 11, 2025

Abstract

The present disclosure provides serial-gate transistors and nonvolatile memory devices including serial-gate transistors. In some embodiments, a nonvolatile memory device includes a plurality of memory blocks, a plurality of pass transistor blocks, and a plurality of gates sequentially arranged in a horizontal direction in a gate region above a semiconductor substrate. Each of the plurality of pass transistor blocks includes a plurality of serial-gate transistors configured to transfer a plurality of driving signals to a corresponding memory block of the plurality of memory blocks. Each of the plurality of serial-gate transistors includes a first source-drain region, a gate region, and a second source-drain region that are sequentially arranged in a horizontal direction at a semiconductor substrate. The plurality of gates are electrically decoupled from each other. A plurality of block selection signals respectively applied to the plurality of gates are controlled independently of each other.

First claim

What is claimed is:

1 . A nonvolatile memory device, comprising:
a plurality of memory blocks; a plurality of pass transistor blocks, each pass transistor block of the plurality of pass transistor blocks comprising a plurality of serial-gate transistors configured to transfer a plurality of driving signals to a corresponding memory block of the plurality of memory blocks, each serial-gate transistor of the plurality of serial-gate transistors comprising:
a first source-drain region, a gate region, and a second source-drain region that are sequentially arranged in a horizontal direction at a semiconductor substrate; and
a plurality of gates that are sequentially arranged in the horizontal direction in the gate region above the semiconductor substrate,
wherein the plurality of gates are electrically decoupled from each other, wherein each gate of the plurality of gates is directly coupled to a corresponding block selection signal of a plurality of block selection signals, and wherein the plurality of gates are controlled independently of each other.

2 . The nonvolatile memory device of claim 1 , wherein:
the plurality of gates comprise a first gate and a second gate, the first gate is adjacent to the first source-drain region in the horizontal direction, the second gate is adjacent to the second source-drain region in the horizontal direction, and a first block selection signal applied to the first gate and a second block selection signal applied to the second gate are controlled independently of each other based on a voltage of a driving signal applied to the first source-drain region and a voltage of a wordline coupled to the second source-drain region.

3 . The nonvolatile memory device of claim 2 , wherein:
based on the voltage of the driving signal being higher than the voltage of the wordline, a voltage of the first block selection signal is higher than a voltage of the second block selection signal, and based on the voltage of the driving signal being lower than the voltage of the wordline, the voltage of the first block selection signal is lower than the voltage of the second block selection signal.

4 . The nonvolatile memory device of claim 2 , wherein, based on the voltage of the driving signal and the voltage of the wordline:
perform a field relaxation function by at least one of the first gate and the second gate, and perform a switching function by at least another one of the first gate and the second gate.

5 . The nonvolatile memory device of claim 2 , wherein, based on the voltage of the driving signal being higher than the voltage of the wordline and each serial-gate transistor of the plurality of serial-gate transistors being in a turned-on state:
a voltage of the first block selection signal is activated to be higher than the voltage of the driving signal, and a voltage of the second block selection signal is activated to be lower than or equal to the voltage of the first block selection signal.

6 . The nonvolatile memory device of claim 2 , wherein, based on the voltage of the driving signal being higher than the voltage of the wordline and each serial-gate transistor of the plurality of serial-gate transistors being in a turned-on state, the second block selection signal is activated after the first block selection signal has been activated.

7 . The nonvolatile memory device of claim 2 , wherein, based on the voltage of the driving signal being lower than the voltage of the wordline and each serial-gate transistor of the plurality of serial-gate transistors being in a turned-off state:
a voltage of the first block selection signal is deactivated to be lower than the voltage of the wordline, and a voltage of the second block selection signal is deactivated to be lower than or equal to the voltage of the first block selection signal.

8 . The nonvolatile memory device of claim 2 , wherein, based on the voltage of the driving signal being lower than the voltage of the wordline and each serial-gate transistor of the plurality of serial-gate transistors being in a turned-off state, the second block selection signal is deactivated after the first block selection signal has been deactivated.

9 . The nonvolatile memory device of claim 2 , wherein, in a program operation:
a selected plurality of serial-gate transistors of a selected pass transistor block corresponding to a selected memory block is set to a turned-on state, and an unselected plurality of serial-gate transistors of an unselected pass transistor block corresponding to an unselected memory block is maintained in a turned-off state.

10 . The nonvolatile memory device of claim 9 , wherein, based on the voltage of the driving signal being increased in the program operation:
a voltage of the first block selection signal applied to the selected pass transistor block is activated to be higher than the voltage of the driving signal, and a voltage of the second block selection signal applied to the selected pass transistor block is activated to be lower than or equal to the voltage of the first block selection signal.

11 . The nonvolatile memory device of claim 9 , wherein, based on the voltage of the driving signal being decreased in the program operation:
a voltage of the second block selection signal applied to the selected pass transistor block is deactivated to be higher than the voltage of the wordline, and a voltage of the first block selection signal applied to the selected pass transistor block is deactivated to be lower than or equal to the voltage of the second block selection signal.

12 . The nonvolatile memory device of claim 9 , wherein, in the program operation:
a voltage of the second block selection signal applied to the unselected pass transistor block is deactivated to be lower than the voltage of the driving signal, and a voltage of the first block selection signal applied to the unselected pass transistor block is deactivated to be higher than or equal to the voltage of the second block selection signal.

13 . The nonvolatile memory device of claim 2 , wherein, in an erase operation:
a selected plurality of serial-gate transistors of a selected pass transistor block corresponding to a selected memory block is maintained in a turned-on state, and an unselected plurality of serial-gate transistors of an unselected pass transistor block corresponding to an unselected memory block is maintained in a turned-off state.

14 . The nonvolatile memory device of claim 13 , wherein, in the erase operation, a voltage of the first block selection signal and a voltage of the second block selection signal applied to the selected pass transistor block are activated to be higher than the voltage of the wordline.

15 . The nonvolatile memory device of claim 13 , wherein, in the erase operation:
a voltage of the first block selection signal applied to the unselected pass transistor block is deactivated to be lower than the voltage of the wordline, and a voltage of the second block selection signal applied to the unselected pass transistor block is deactivated to be higher than or equal to the voltage of the first block selection signal.

16 . The nonvolatile memory device of claim 2 , wherein:
the first source-drain region comprises a first region and a second region, the driving signal is applied to the first region of the first source-drain region, the first region is formed by doping the semiconductor substrate with a first dopant density, the second region is formed by doping the semiconductor substrate between the first region and the first gate with

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Cheonan
• Song Kiwhan
• Choo Gyosoo
• Sung Sukkang

Classifications

• G11C16/08

  Address circuits; Decoders; Word-line control circuits · CPC title

• H10B43/27

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title

• H10B41/27

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title

• H10B43/40

  characterised by the peripheral circuit region · CPC title

• H10B41/40 Primary

  characterised by the peripheral circuit region · CPC title