Semiconductor memory device

Patent metadata

Field	Value
Publication number	US-10347318-B2
Application number	US-201715709674-A
Country	US
Kind code	B2
Filing date	Sep 20, 2017
Priority date	Mar 20, 2017
Publication date	Jul 9, 2019
Grant date	Jul 9, 2019

Abstract

A semiconductor memory device includes a memory cell array and a row decoder disposed in a first direction over a substrate and a plurality of coupling lines for electrically coupling the memory cell array and the row decoder. Each of the coupling lines includes a first conductive line disposed in the first direction; a second conductive line disposed parallel to the first conductive line; and a pad coupling the first conductive line and the second conductive line, and coupled to the memory cell array or the row decoder through a contact plug. The coupling lines are routed from both sides of the pad in the first direction.

First claim

What is claimed is:

1. A semiconductor memory device comprising:
a memory cell array and a row decoder disposed in a first direction over a substrate; and
a plurality of coupling lines for electrically coupling the memory cell array and the row decoder,
wherein each of the coupling lines comprises:
a first conductive line disposed in the first direction;
a second conductive line disposed parallel to the first conductive line; and
a pad coupling between the first conductive line and the second conductive line, and electrically coupled to the memory cell array or the row decoder through a contact plug,

wherein the coupling lines are routed from both sides of the respective pads in the first direction, and
wherein the pads of the coupling lines are disposed in a direction oblique to the first direction and a second direction perpendicular to the first direction.

2. The semiconductor memory device according to claim 1 , wherein the first conductive line and the second conductive line extend in opposite directions from the pad.

3. The semiconductor memory device according to claim 1 , wherein the coupling lines are disposed such that the respective pads do not overlap with pads of adjacent coupling lines in the second direction.

4. The semiconductor memory device according to claim 3 , wherein the pad of each of the coupling lines overlaps with the first conductive line or the second conductive line of the adjacent coupling line in the second direction.

5. The semiconductor memory device according to claim 1 ,
wherein the coupling lines include n (n is a natural number equal to or greater than 3) number of coupling lines which are disposed sequentially in the second direction, and
wherein the second conductive line of a (k−1)th (k is a natural number equal to or greater than n−2) coupling line among the coupling lines is disposed on the same line as the first conductive line of a (k+1)th coupling line.

6. The semiconductor memory device according to claim 1 , wherein the pad of each of the coupling lines comprises:
a quadrangular frame-shaped structural body coupled between the first conductive line and the second conductive line; and
an internal line pattern disposed in the first direction, in an internal region surrounded by the quadrangular frame-shaped structural body.

7. The semiconductor memory device according to claim 6 , wherein the quadrangular frame-shaped structural body comprises:
a first line pattern extending from an end of the first conductive line in the first direction, and having a width substantially the same as the first conductive line;
a second line pattern extending from an end of the second conductive line in the first direction, and having a width substantially the same as the second conductive line;
a third line pattern extending from an end of the first line pattern to the second line pattern in the second direction; and
a fourth line pattern extending from an end of the second line pattern to the first line pattern in the second direction.

8. The semiconductor memory device according to claim 7 , wherein a spacing between the first line pattern and the internal line pattern in the second direction and a spacing between the second line pattern and the internal line pattern in the second direction are the same as a spacing between the coupling lines.

9. The semiconductor memory device according to claim 1 , wherein the pad has a rectangular structure.

10. The semiconductor memory device according to claim 1 , wherein at least one of the first conductive line and the second conductive line extends from both sides of the pad, and the first conductive line and the second conductive line overlap at least partially in the second direction.

11. The semiconductor memory device according to claim 10 ,
wherein each of the coupling lines further comprises a third conductive line which is disposed parallel to the first and second conductive lines between the first conductive line and the second conductive line which overlap in the second direction, and
wherein a spacing between the first conductive line and the third conductive line in the second direction and a spacing between the second conductive line and the third conductive line in the second direction are the same as a spacing between the coupling lines.

12. A semiconductor memory device comprising:
a first sub memory cell array and a second sub memory cell array disposed adjacent to each other in a first direction;
a first sub row decoder disposed between the first sub memory cell array and the second sub memory cell array; and
coupling lines disposed over the first and second sub memory cell arrays and the first sub row decoder,
wherein each of the coupling lines comprises a first conductive line which is disposed in the first direction, a second conductive line which is disposed parallel to the first conductive line, and a pad which is coupled between the first conductive line and the second conductive line and is electrically coupled to the first sub row decoder through a first contact plug, and
wherein each of the coupling lines is routed from both sides of the corresponding pad in the first direction and is electrically coupled to the first sub memory cell array and the second sub memory cell array.

13. The semiconductor memory device according to claim 12 , wherein the first sub row decoder comprises:
a plurality of pass transistors having sources which are respectively coupled to the first contact plugs and drains which are respectively coupled to corresponding control gate lines.

14. The semiconductor memory device according to claim 12 ,
wherein each of the first sub memory cell array and the second sub memory cell array comprises a plurality of gate lines which are stacked, and
wherein each of the coupling lines is electrically coupled with one of some gate lines of the first sub memory cell array through a corresponding second contact plug, and is electrically coupled with one of some gate lines of the second sub memory cell array through a corresponding third contact plug.

15. The semiconductor memory device according to claim 14 , further comprising:
a second sub row decoder disposed adjacent to the first sub row decoder in the first direction with the first sub memory cell array interposed therebetween, and electrically coupled with remaining gate lines of the first sub memory cell array; and
a third sub row decoder disposed adjacent to the first sub row decoder in the first direction with the second sub memory cell array interposed therebetween, and electrically coupled with remaining gate lines of the second sub memory cell array.

16. A semiconductor memory device comprising:
a plurality of coupling lines each comprising a first conductive line which is disposed in a first direction, and a second conductive line which is disposed parallel to the first conductive line and a pad,
wherein the pad of each of the coupling lines comprises:
a quadrangular frame-shaped structural body coupled between the first conductive line and the second conductive line; and
an internal line pattern disposed in the first direction, in an internal region surrounded by the quadrangular frame-shaped structural body, and

wherein the pads of the coupling lines are disposed in a direction oblique to the first direction and a second direction perpendicular to the first direction.

17. The semiconductor memory device according to claim 16 , wherein the quadrangular frame-shaped structural body comprises:
a first line pattern extending from an end of the first conductive line i

Assignees

• Sk Hynix Inc

Inventors

• Kim Jeong-Hwan
• Kim Jin-Ho
• Sung Sang-Hyun

Classifications

• G11C8/14 Primary

  Word line organisation; Word line lay-out · CPC title

• G11C16/0441

  comprising cells containing multiple floating gate devices, e.g. separate read-and-write FAMOS transistors with connected floating gates · CPC title

• G11C7/18

  Bit line organisation; Bit line lay-out · CPC title

• H01L27/11582

  Electricity · mapped topic

• G11C8/10 Primary

  Decoders · CPC title