Three dimensional semiconductor memory devices

Patent metadata

Field	Value
Publication number	US-10319738-B2
Application number	US-201715844188-A
Country	US
Kind code	B2
Filing date	Dec 15, 2017
Priority date	Apr 5, 2017
Publication date	Jun 11, 2019
Grant date	Jun 11, 2019

Abstract

A three-dimensional semiconductor memory device includes a cell string vertically extending from a top surface of a substrate and having first and second cell transistors, first and second word lines connected to gate electrodes of the first and second cell transistors respectively, a first pass transistor connecting the first word line to a row decoder, and a second pass transistor connecting the second word line to the row decoder. The first pass transistor includes a plurality of first sub-transistors connected in parallel between the first word line and the row decoder.

First claim

What is claimed is:

1. A three-dimensional semiconductor memory device comprising:
a cell string vertically extending from a top surface of a substrate and including first and second cell transistors;
first and second word lines connected to gate electrodes of the first and second cell transistors, respectively;
a first pass transistor connecting the first word line to a row decoder; and
a second pass transistor connecting the second word line to the row decoder, wherein
the first pass transistor comprises a plurality of first sub-transistors connected in parallel between the first word line and the row decoder.

2. The three-dimensional semiconductor memory device of claim 1 , wherein the first sub-transistors each have the same size as that of the second pass transistor.

3. The three-dimensional semiconductor memory device of claim 1 , wherein the first sub-transistors have the same gate length and the same gate width.

4. The three-dimensional semiconductor memory device of claim 1 , wherein the first sub-transistors have the same gate length and different gate widths.

5. The three-dimensional semiconductor memory device of claim 1 , wherein:
the first word line is positioned from the top surface of the substrate at a first distance, and
the second word line is positioned from the top surface of the substrate at a second distance less than the first distance.

6. The three-dimensional semiconductor memory device of claim 1 , wherein the cell string comprises:
an electrode structure including a plurality of word lines vertically stacked on the substrate, the plurality of word lines including the first and second word lines;
a vertical semiconductor pillar having a width that increases as approaching its top from its bottom and penetrating the electrode structure; and
a data storage layer between the electrode structure and the vertical semiconductor pillar.

7. The three-dimensional semiconductor memory device of claim 1 , wherein the cell string comprises:
a lower electrode structure including a plurality of lower electrodes vertically stacked on the substrate;
a lower semiconductor pillar penetrating the lower electrode structure;
an upper electrode structure including a plurality of upper electrodes vertically stacked on the lower electrode structure; and
an upper semiconductor pillar penetrating the upper electrode structure and connected to the lower semiconductor pillar, wherein
each of the lower and upper semiconductor pillars has a width that increases as approaching its top from its bottom, and
each of the lower and upper electrode structures comprises the first and second word lines.

8. The three-dimensional semiconductor memory device of claim 1 , further comprising:
a third cell transistor connected in series to the second cell transistor;
a third word line connected to a gate electrode of the third cell transistor; and
a third pass transistor connecting the third word line to the row decoder, wherein:
the first to third word lines are sequentially stacked on the substrate, and
the third pass transistor has a size greater than that of the first pass transistor.

9. The three-dimensional semiconductor memory device of claim 8 , wherein:
the third pass transistor comprises a plurality of second sub-transistors connected in parallel between the third word line and the row decoder, and
a number of the second sub-transistors constituting the third pass transistor being different from that of the first sub-transistors constituting the first pass transistor.

10. A three-dimensional semiconductor memory device comprising:
a substrate including a peripheral circuit region and a cell array region;
an electrode structure including word lines vertically stacked on the substrate of the cell array region, the word lines including a lower word line positioned from a top surface of the substrate at a first distance and an upper word line positioned from the top surface of the substrate at a second distance greater than the first distance;
a first pass transistor disposed on the substrate of the peripheral circuit region and connecting a row decoder to the lower word line; and
a second pass transistor disposed on the substrate of the peripheral circuit region and connecting the row decoder to the upper word line, wherein
the first pass transistor comprises m first sub-transistors connected to the lower word line, and the second pass transistor comprises n second sub-transistors connected to the upper word line, wherein n and m are natural numbers.

11. The three-dimensional semiconductor memory device of claim 10 , further comprising:
a vertical semiconductor pillar penetrating the electrode structure; and
a data storage layer between the electrode structure and the vertical semiconductor pillar, wherein
the vertical semiconductor pillar has a width that increases as approaching its top from its bottom.

12. The three-dimensional semiconductor memory device of claim 10 , wherein:
the first sub-transistors are connected to each other in parallel between the row decoder and the lower word line, and
the second sub-transistors are connected to each other in parallel between the row decoder and the upper word line.

13. The three-dimensional semiconductor memory device of claim 10 , wherein the first and second sub-transistors have the same gate length and the same gate width.

14. The three-dimensional semiconductor memory device of claim 13 , wherein n and m are different natural numbers from each other.

15. The three-dimensional semiconductor memory device of claim 13 , wherein the first pass transistor has an effective gate width different from that of the second pass transistor.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Chang-Bum
• Kim Sunghoon

Classifications

• G11C16/0483 Primary

  comprising cells having several storage transistors connected in series · CPC title

• G11C8/08 Primary

  Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines · CPC title

• G11C8/14 Primary

  Word line organisation; Word line lay-out · CPC title

• G11C16/107

  Programming all cells in an array, sector or block to the same state prior to flash erasing · CPC title

• G11C16/08

  Address circuits; Decoders; Word-line control circuits · CPC title