Field relaxation thin film transistor, method of manufacturing the same and display apparatus including the transistor

Patent metadata

Field	Value
Publication number	US-2017200740-A1
Application number	US-201715460161-A
Country	US
Kind code	A1
Filing date	Mar 15, 2017
Priority date	Oct 16, 2013
Publication date	Jul 13, 2017
Grant date	—

Abstract

A thin film transistor includes a semiconductor pattern formed on a substrate, the semiconductor pattern being formed of an oxide semiconductor and including a source area, a drain area, and an intermediate area that is formed between the source area and the drain area and includes a plurality of first areas and a second area having higher conductivity than the first areas; a first insulating pattern formed to cover at least the first areas; a second insulating film formed to face the second area, the source area and the drain area; a gate electrode formed on the semiconductor pattern and insulated from the semiconductor pattern by the first insulating pattern and the second insulating film; and source and drain electrodes insulated from the gate electrode and being in contact with the source area and the drain area.

First claim

What is claimed is:

1 . A method of manufacturing a thin film transistor, the method comprising:
forming on a substrate a semiconductor pattern formed of an oxide semiconductor; forming a first insulating pattern formed of an oxide, on a first area that is a portion of an intermediate area of the semiconductor pattern; forming a second insulating film formed of a nitride to cover the first insulating pattern and the semiconductor pattern; forming a gate electrode on at least the first insulating pattern; and forming source and drain electrodes in contact with edges of the semiconductor pattern.

2 . The method of claim 1 , wherein the second insulating film is formed of a silicon nitride and the second insulating film is formed by using a reactant gas comprising hydrogen (H).

3 . A thin film transistor comprising:
a semiconductor pattern formed on a substrate, the semiconductor pattern being formed of an oxide semiconductor and including a source area, a drain area, and an intermediate area that is formed between the source area and the drain area and includes a plurality of first areas and a second area having higher conductivity than the first areas; a first insulating pattern formed to cover at least the first areas; a second insulating film formed to face the second area, the source area and the drain area; a gate electrode formed on the semiconductor pattern and insulated from the semiconductor pattern by the first insulating pattern and the second insulating film; and source and drain electrodes insulated from the gate electrode and being in contact with the source area and the drain area; wherein two or more gate electrodes are formed, and one of the gate electrodes is arranged to face the plurality of first areas and the second area.

4 . The thin film transistor of claim 3 , wherein the first area is a channel area.

5 . The thin film transistor of claim 3 , wherein the intermediate area comprises the plurality of first areas and at least one second area.

6 . The thin film transistor of claim 5 , wherein the first area and the second area are alternately arranged in the intermediate area.

7 . The thin film transistor of claim 5 , wherein the first area is arranged adjacently to the source are and the drain area.

8 . The thin film transistor of claim 3 , wherein the oxide semiconductor comprises at least one oxide selected from a group of zinc (Zn), indium (In), gallium (Ga), tin (Sn), cadmium (Cd), germanium (Ge), and hafnium (Hf).

9 . The thin film transistor of claim 3 , wherein the first insulating pattern is formed of an oxide and the second insulating film is formed of a nitride.

10 . A display apparatus comprising:
a substrate divided into a display area to display images and a non-display area around the display area; a driving circuit unit arranged on the non-display area, the driving circuit unit comprising a thin film transistor and being electrically coupled to the display area to drive the display area, wherein the thin film transistor comprising: a semiconductor pattern formed on a substrate, the semiconductor pattern being formed of an oxide semiconductor and including a source area, a drain area, and an intermediate area that is formed between the source area and the drain area and includes a plurality of first areas and a second area having higher conductivity than the first areas; a first insulating pattern formed to cover at least the first areas; a second insulating film formed to face the second area, the source area and the drain area; a gate electrode formed on the semiconductor pattern and insulated from the semiconductor pattern by the first insulating pattern and the second insulating film; and source and drain electrodes insulated from the gate electrode and being in contact with the source area and the drain area; wherein two or more gate electrodes are formed, and one of the gate electrodes is arranged to face the plurality of first areas and the second area.

11 . The display apparatus of claim 10 , wherein the first area is a channel area.

12 . The display apparatus of claim 10 , wherein the intermediate area comprises the plurality of first areas and at least one second area.

13 . The display apparatus of claim 12 , wherein the first area and the second area are alternately arranged in the intermediate area.

14 . The display apparatus of claim 12 , wherein the first area is arranged adjacently to the source are and the drain area.

15 . The display apparatus of claim 10 , wherein the oxide semiconductor comprises at least one oxide selected from a group of zinc (Zn), indium (In), gallium (Ga), tin (Sn), cadmium (Cd), germanium (Ge), and hafnium (Hf).

16 . The display apparatus of claim 10 , wherein two or more gate electrodes are formed, and one of the gate electrodes is arranged to face one of the first areas.

17 . The display apparatus of claim 10 , wherein the first insulating pattern is formed of an oxide and the second insulating film is formed of a nitride.

Assignees

• Samsung Display Co Ltd

Inventors

• Kang Su-Hyoung
• Cho Seung-Hwan
• Khang Yoon-Ho
• Lee Jong-Chan

Classifications

• H10D30/6719

  having significant overlap between the lightly-doped drains and the gate electrodes, e.g. gate-overlapped LDD [GOLDD] TFTs · CPC title

• H01L27/3248

  Electricity · mapped topic

• H01L29/7869

  Electricity · mapped topic

• H01L27/124 Primary

  Electricity · mapped topic

• H10D30/6755

  Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate · CPC title