Integrated circuit device having inclined structures

Patent metadata

Field	Value
Publication number	US-12464810-B2
Application number	US-202217569795-A
Country	US
Kind code	B2
Filing date	Jan 6, 2022
Priority date	May 18, 2021
Publication date	Nov 4, 2025
Grant date	Nov 4, 2025

Abstract

An integrated circuit device includes: a first fin-type active region and a second fin-type active region that extend on a substrate in a straight line in a first horizontal direction and are adjacent to each other in the first horizontal direction; a fin isolation region arranged between the first fin-type active region and the second fin-type active region on the substrate and including a fin isolation insulation structure extending in a second horizontal direction perpendicular to the first horizontal direction; and a plurality of gate lines extending on the first fin-type active region in the second horizontal direction, wherein a first gate line that is closest to the fin isolation region from among the plurality of gate lines is inclined to be closer to a center of the fin isolation region in the first horizontal direction from a lowermost surface to an uppermost surface of the first gate line.

First claim

What is claimed is:

1 . An integrated circuit device comprising:
a first fin-type active region and a second fin-type active region, the first fin-type active region and the second fin-type active region extending on a substrate in a straight line in a first horizontal direction, the first fin-type active region and the second fin-type active region adjacent to each other in the first horizontal direction; a fin isolation region on the substrate and between the first fin-type active region and the second fin-type active region, the fin isolation region comprising a fin isolation insulation structure extending in a second horizontal direction that is perpendicular to the first horizontal direction; a plurality of gate lines on the first fin-type active region and extending in the second horizontal direction,
wherein a first gate line that is closest to the fin isolation region from among the plurality of gate lines is inclined in the first horizontal direction, an inclination from a lowermost surface of the first gate line to an uppermost surface of the first gate line being towards a center of the fin isolation region, and
wherein the fin isolation insulation structure includes:
a fin isolation insulation pattern filling a space between the first fin-type active region and the second fin-type active region;
a fin isolation insulation liner contacting an upper surface of the fin isolation insulation pattern and covering a sidewall of the first gate line, wherein sidewalls of the fin isolation insulation liner are inclined in the first horizontal direction and an inclination from a lower portion of the sidewalls to an upper portion of the sidewalls is towards the center of the fin isolation region; and
a fin isolation gap-fill insulation layer between the first fin-type active region and the second fin-type active region and filling an upper space on the fin isolation insulation liner,
wherein a lowermost surface of the fin isolation insulation liner and a lowermost surface of the fin isolation gap-fill insulation layer are lower than the upper surface of the fin isolation insulation pattern; and

a plurality of insulation capping lines, wherein each insulation capping line of the plurality of insulation capping lines respectively covers upper surfaces of the plurality of gate lines, and a sidewall of the insulation capping line on the upper surface of the first gate line contacts the fin isolation insulation liner.

2 . The integrated circuit device of claim 1 , wherein the plurality of gate lines comprise a second gate line which is most adjacent to the first gate line and a third gate line which is adjacent to the second gate line and spaced apart from the first gate line in the first horizontal direction with the second gate line between the first gate line and the third gate line, and
in the first horizontal direction, a first gap between a first upper surface of the first gate line and a second upper surface of the second gate line is greater than a second gap between the second upper surface of the second gate line and a third upper surface of the third gate line.

3 . The integrated circuit device of claim 1 , wherein the first gate line covers a fin upper surface of the first fin-type active region and sidewalls of the first fin-type active region, the sidewalls faces facing the fin isolation region, and the sidewalls are covered by the first gate line from among a plurality of sidewalls of the first fin-type active region.

4 . The integrated circuit device of claim 1 , further comprising:
a source/drain region on the first fin-type active region between the first gate line and a second gate line which is most adjacent to the first gate line; and a source/drain contact between the first gate line and the second gate line, extending in a vertical direction, and connected to the source/drain region,
wherein a first distance between a first upper surface of the first gate line and the source/drain contact in the first horizontal direction is greater than a second distance between a second upper surface of the second gate line and the source/drain contact.

5 . The integrated circuit device of claim 1 ,
wherein the fin isolation insulation liner includes an insulation material not included in the fin isolation insulation pattern, and the fin isolation gap-fill insulation layer includes an insulation material not included in the fin isolation insulation liner.

6 . The integrated circuit device of claim 1 , further comprising:
a first insulation spacer and a second insulation spacer, the first insulation spacer and the second insulation spacer covering both sidewalls of the first gate line in the first horizontal direction, wherein
the first insulation spacer overlaps the first fin-type active region in a vertical direction,
the second insulation spacer overlaps the fin isolation region in the vertical direction, and
each insulation capping line of the plurality of insulation capping lines on the upper surface of the first gate line covers upper surfaces of the first insulation spacer and the second insulation spacer.

7 . The integrated circuit device of claim 1 , further comprising:
a first insulation spacer and a second insulation spacer, the first insulation spacer and the second insulation spacer covering both sidewalls of the first gate line in the first horizontal direction, wherein
a lowermost surface of the first insulation spacer contacts a fin upper surface of the first fin-type active region,
a lowermost surface of the second insulation spacer contacts the fin isolation insulation pattern, and
each insulation capping line of the plurality of insulation capping lines on the upper surface of the first gate line covers upper surfaces of the first insulation spacer and the second insulation spacer.

8 . The integrated circuit device of claim 1 ,
wherein the lowermost surface of the fin isolation insulation liner is lower than the lowermost surface of the first gate line.

9 . An integrated circuit device comprising:
a first logic cell on a substrate; a second logic cell spaced apart from the first logic cell on the substrate in a first horizontal direction; a fin isolation region between the first logic cell and the second logic cell, the fin isolation region including a fin isolation insulation structure extending in a second horizontal direction that is perpendicular to the first horizontal direction; a first fin-type active region extending in the first logic cell in the first horizontal direction; a second fin-type active region extending in the second logic cell in the first horizontal direction; a plurality of first gate lines extending on the first fin-type active region in the second horizontal direction,
wherein an outermost first gate line that is closest to the fin isolation region from among the plurality of first gate lines is inclined in the first horizontal direction, an inclination from a first lowermost surface of the outermost first gate line to a first uppermost surface of the outermost first gate line being towards a center of the fin isolation region, and
wherein the fin isolation insulation structure includes:
a fin isolation insulation pattern filling a space between the first fin-type active region and the second fin-type active region;
a fin isolation insulation liner contacting an upper surface of the fin isolation insulation pattern and covering a sidewall of the outermost first gate line, wherein sidewalls of the fin isolation insulation liner are inclined in the first horizontal direction and an inclination from a lower portion of the sidewalls to an upper portion of the sidewalls is towards the center of the fin isolation region; and
a fin iso

Assignees

• Samsung Electronics Co Ltd

Inventors

• Park Juhun
• Bae Deokhan
• Um Myungyoon
• Lee Yuri
• Jung Yoonyoung
• Hong Sooyeon

Classifications

• H10W10/17

  formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10W10/014

  using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10D30/502

  characterised by the stacked channels · CPC title

• H10D84/832

  comprising IGFETs having stacked nanowire, nanosheet or nanoribbon channels · CPC title

• H10D62/121

  oriented parallel to substrates · CPC title