Semiconductor device including a semiconductor extension layer between active regions

Patent metadata

Field	Value
Publication number	US-10373953-B2
Application number	US-201615159464-A
Country	US
Kind code	B2
Filing date	May 19, 2016
Priority date	May 19, 2015
Publication date	Aug 6, 2019
Grant date	Aug 6, 2019

Abstract

A semiconductor device includes a first active region and a second active region, which are disposed in a semiconductor substrate and have side surfaces facing each other, an isolation pattern disposed between the first and second active regions, a semiconductor extension layer disposed between the first and second active regions, a first source/drain semiconductor layer disposed on the first active region, and a second source/drain semiconductor layer disposed on the second active region. The facing side surfaces of the first and second active regions are closer to the semiconductor extension layer than the isolation pattern.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a first active region and a second active region, which are disposed in a semiconductor substrate and have side surfaces facing each other;
an isolation pattern disposed between the first and second active regions;
a semiconductor extension layer disposed between the first and second active regions;
a first source/drain semiconductor layer disposed on the first active region; and
a second source/drain semiconductor layer disposed on the second active region;
wherein the semiconductor extension layer is disposed between the first active region and the isolation pattern and between the second active region and the isolation pattern.

2. The semiconductor device of claim 1 , wherein the semiconductor extension layer is in contact with the side surfaces of the first and second active regions.

3. The semiconductor device of claim 1 , wherein a level of an upper end of the semiconductor extension layer is higher than a level of an upper surface of the isolation pattern relative to the semiconductor substrate.

4. The semiconductor device of claim 1 , wherein the semiconductor extension layer extends under the isolation pattern relative to the semiconductor substrate.

5. The semiconductor device of claim 1 , wherein the first source/drain semiconductor layer is disposed in a first recessed area in the first active region.

6. The semiconductor device of claim 5 , wherein a level of an upper end of the semiconductor extension layer is higher than a level of a bottom of the first recessed area relative to the semiconductor substrate.

7. The semiconductor device of claim 5 , wherein a level of a bottom of the semiconductor extension layer is lower than a level of a bottom of the first recessed area relative to the semiconductor substrate.

8. The semiconductor device of claim 1 , wherein:
the semiconductor extension layer is a first epitaxial layer; and
the first and second source/drain semiconductor layers are second epitaxial layers different from the first epitaxial layer.

9. The semiconductor device of claim 1 , wherein the facing side surfaces of the first and second active regions are closer to the semiconductor extension layer than the isolation pattern.

10. A semiconductor device, comprising:
a first active region and a second active region, which are disposed in a semiconductor substrate and have side surfaces facing each other;
an isolation pattern disposed between the first and second active regions;
a semiconductor extension layer disposed between the first and second active regions;
a first source/drain semiconductor layer disposed on the first active region; and
a second source/drain semiconductor layer disposed on the second active region;
wherein the first source/drain semiconductor layer is disposed in a first recessed area in the first active region; and
wherein a level of an upper end of the semiconductor extension layer is higher than a level of a bottom of the first recessed area relative to the semiconductor substrate.

11. A semiconductor device, comprising:
a first active region and a second active region, which are disposed in a semiconductor substrate and have side surfaces facing each other;
an isolation pattern disposed between the first and second active regions;
a semiconductor extension layer disposed between the first and second active regions;
a first source/drain semiconductor layer disposed on the first active region; and
a second source/drain semiconductor layer disposed on the second active region;
wherein the first source/drain semiconductor layer is disposed in a first recessed area in the first active region; and
wherein a level of a bottom of the semiconductor extension layer is lower than a level of a bottom of the first recessed area relative to the semiconductor substrate.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Sungmin
• Kang Jisu
• Park Jaehyun
• Shin Heonjong
• Lee Yuri

Classifications

• H01L27/088

  Electricity · mapped topic

• H01L21/823481

  Electricity · mapped topic

• H01L21/823431

  Electricity · mapped topic

• H01L29/0653

  Electricity · mapped topic

• H01L29/785

  Electricity · mapped topic