Fin field effect transistor (FinFET) device and method for forming the same

Patent metadata

Field	Value
Publication number	US-9401415-B2
Application number	US-201414181320-A
Country	US
Kind code	B2
Filing date	Feb 14, 2014
Priority date	Feb 14, 2014
Publication date	Jul 26, 2016
Grant date	Jul 26, 2016

Abstract

Embodiments for forming a fin field effect transistor (FinFET) device structure are provided. The FinFET device structure includes a fin structure extending above a substrate and a gate dielectric layer formed over the fin structure. The FinFET device structure also includes a gate electrode formed on the gate dielectric layer. The FinFET device structure further includes a number of gate spacers formed on sidewalls of the gate electrode. The gate spacers are in direct contact with the fin structure.

First claim

What is claimed is:

1. A fin field effect transistor (FinFET) device structure, comprising:
a fin structure extending above a substrate along a lengthwise direction thereof;
a gate dielectric layer formed over the fin structure;
a gate electrode formed on the gate dielectric layer;
a plurality of gate spacers formed on sidewalls of the gate electrode, wherein the gate spacers are in direct contact with the fin structure; and
a source/drain (S/D) stressor formed adjacent to the gate spacers,
wherein the gate dielectric layer has a top surface and a bottom surface, and a bottom width of the bottom surface of the gate dielectric layer is smaller than a top width of the top surface of the gate dielectric layer when seen from a cross sectional view along the lengthwise direction of the fin structure,
wherein the gate dielectric layer has a trapezoid shape or L-shape,
wherein sidewalls of the gate spacers are not parallel to sidewalls of the gate electrode, and
wherein the sidewalls of the gate dielectric layer is sloped to a top surface of the fin structure.

2. The fin field effect transistor (FinFET) device structure as claimed in claim 1 , wherein the gate spacers have a top portion adjacent to the gate electrode and a bottom portion adjacent to the gate dielectric layer, and a bottom width of the bottom portion of the gate spacers is larger than a top width of the top portion of the gate spacers.

3. The fin field effect transistor (FinFET) device structure as claimed in claim 2 , wherein a ratio of the top width of the top portion of the gate spacers to the bottom width of the bottom portion of the gate spacers is in a range from about 0.1 to about 1.

4. The fin field effect transistor (FinFET) device structure as claimed in claim 1 , wherein the gate dielectric layer is a high-k dielectric layer and the gate electrode is a metal gate electrode.

5. The fin field effect transistor (FinFET) device structure as claimed in claim 1 , wherein the gate dielectric layer is an oxide layer and the gate electrode is a polysilicon gate electrode.

6. The fin field effect transistor (FinFET) device structure as claimed in claim 1 , wherein the bottom width of the bottom surface of the gate dielectric layer is smaller than a width of a bottom surface of the gate electrode.

7. The fin field effect transistor (FinFET) device structure as claimed in claim 1 , wherein the S/D stressor extends into the fin structure.

8. The fin field effect transistor (FinFET) device structure as claimed in claim 1 , further comprising:
an isolation structure fowled between the substrate and the fin structure, wherein the S/D stressor extends into the isolation structure.

9. A fin field effect transistor (FinFET) device structure, comprising:
a substrate;
a fin structure extending above the substrate along a lengthwise direction thereof;
a gate dielectric layer formed over the fin;
a gate electrode formed on the gate dielectric layer;
a plurality of gate spacers formed on sidewalls of the gate electrode, wherein the gate spacers comprises a protruded bottom portion adjacent to the gate dielectric layer; and
a source/drain (S/D) stressor formed adjacent to the gate spacers, wherein the fin structure is formed between the gate dielectric layer and S/D stressor,
wherein the gate dielectric layer has a top surface and a bottom surface, and a bottom width of the bottom surface of the gate dielectric layer is smaller than a top width of the top surface of the gate dielectric layer when seen from a cross sectional view along the lengthwise direction of the fin structure,
wherein the gate dielectric layer has a trapezoid shape or L-shape,
wherein sidewalls of the gate spacers are not parallel to sidewalls of the gate electrode, and
wherein the sidewalls of the gate dielectric layer is sloped to a top surface of the fin structure.

10. The fin field effect transistor (FinFET) device structure as claimed in claim 9 , wherein the gate spacers are in direct contact with the fin structure.

11. The fin field effect transistor (FinFET) device structure as claimed in claim 9 , further comprising:
an isolation structure formed between the substrate and the fin, wherein the S/D stressor extends into the isolation structure.

12. The fin field effect transistor (FinFET) device structure as claimed in claim 9 , wherein the bottom width of the bottom surface of the gate dielectric layer is smaller than a width of a bottom surface of the gate electrode.

13. The fin field effect transistor (FinFET) device structure as claimed in claim 9 , wherein the gate spacers further comprises a top portion adjacent to the gate electrode, and a bottom width of the protruded bottom portion of the gate spacers is larger than a top width of the top portion of the gate spacers.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chang Che-Cheng
• Chen chang-yin
• Lin Jr-Jung
• Lin Chih-Han
• Chang Yung-Jung

Classifications

• H10D30/62

  Fin field-effect transistors [FinFET] · CPC title

• H10D30/024 Primary

  of fin field-effect transistors [FinFET] · CPC title

• H10D62/822

  comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions · CPC title

• H10D64/018

  Spacers formed inside holes at the prospective gate locations, e.g. holes left by removing dummy gates · CPC title

• H10D64/017

  using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes · CPC title