Simple contact over gate on active area

Patent metadata

Field	Value
Publication number	US-10529624-B2
Application number	US-201715819109-A
Country	US
Kind code	B2
Filing date	Nov 21, 2017
Priority date	Nov 21, 2017
Publication date	Jan 7, 2020
Grant date	Jan 7, 2020

Abstract

Semiconductor devices and methods are provided to fabricate FET devices having overlapping gate and source/drain contacts while preventing electrical shorts between the overlapping gate and source/drain contacts. For example, a semiconductor device includes a plurality of semiconductor fins patterned in a starting semiconductor substrate; a set of gate structures formed on the starting semiconductor substrate; a set of spacers formed around each of the set of gate structures; a source and drain region grown around the plurality of fins; a conductive metal material on the source and drain region, an insulating material is configured to be deposited over an upper surface of the conductive metal material and the gate structure; and a plurality of contacts in the insulator material. The plurality of contacts is formed such that a bottom surface of the plurality of contacts is in contact with at least a portion of the upper surface of the gate structure. The plurality of contacts is further formed such that the plurality of contacts are positioned in at least a portion of the insulating material configured to be deposited over the upper surface of the conductive metal material.

First claim

What is claimed is:

1. A method for fabricating a semiconductor device, comprising:
forming a field effect transistor (FET) device on a semiconductor substrate, the FET device comprising a source/drain layer, a first insulator layer on the source/drain layer and a gate structure comprising a gate electrode layer, a gate capping layer, and a gate sidewall spacer;
etching at least a portion of the first insulator layer to provide an opening having an exposed top surface of the source/drain layer, wherein the etching of at least a portion of the first insulator layer is selective to the gate structure;
depositing a conductive metal material to completely fill the opening;
patterning an upper surface of the conductive metal material to a target width of the conductive metal material and recessing the upper surface of the conductive metal material down to a target depth in the conductive metal material to provide a recessed opening;
forming a planarized second insulator layer on a top surface of the gate structure and to completely fill the recessed opening;
forming a metal contact opening in the planarized second insulator layer to an upper portion of the recessed opening and to at least a portion of a top surface of the gate structure below the gate capping layer; and
depositing an interconnect conductor to completely fill the metal contact opening to a top surface of the second insulator layer.

2. The method of claim 1 , wherein the FET device comprises a FinFET device.

3. The method of claim 1 , wherein the source/drain layer is an epitaxially grown raised source drain on the semiconductor substrate.

4. The method of claim 1 , wherein the first insulator layer and the second insulator layer comprise the same or different material.

5. The method of claim 1 , wherein the conductive metal material is tungsten.

6. The method of claim 1 , wherein the gate structure further comprises a gate dielectric layer.

7. The method of claim 6 , wherein the gate dielectric layer comprises a high-k dielectric material.

8. The method of claim 1 , wherein the patterning comprises applying an etch mask on the FET device to expose the target width of the upper surface of the conductive metal material.

9. The method of claim 1 , wherein patterning the upper surface of the conductive metal material includes patterning the upper surface of the conductive metal material to a width of about 20 nm to about 40 nm.

10. The method of claim 1 , wherein recessing the upper surface of the conductive metal material down to the target depth in the conductive metal material comprises selectively etching the conductive metallic material, wherein the etching of the upper surface of the conductive metal material is selective to the gate structure.

11. The method of claim 1 , wherein recessing the conductive metal material includes recessing the conductive metal material to between about 20 nm to about 50 nm in height.

12. The method of claim 8 , further comprising stripping the etch mask after recessing.

13. The method of claim 1 , wherein the upper portion in the recessed opening of the gate contact opening is above the conductive metal material.

14. The method of claim 1 , wherein the interconnect conductor is copper.

Assignees

• IBM

Inventors

• Leobandung Effendi

Classifications

• H10W20/4441

  the principal metal being a refractory metal · CPC title

• H10W20/4421

  the principal metal being copper · CPC title

• H10W20/0698

  Local interconnections · CPC title

• H10W20/083

  the openings being via holes penetrating underlying conductors · CPC title

• H10W20/20

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title