Semicondcutor device including a semiconductor extension layer between active regions

Patent metadata

Field	Value
Publication number	US-10825810-B2
Application number	US-201916444683-A
Country	US
Kind code	B2
Filing date	Jun 18, 2019
Priority date	May 19, 2015
Publication date	Nov 3, 2020
Grant date	Nov 3, 2020

Abstract

A semiconductor device includes a first active region and a second active region, which are disposed in a semiconductor substrate and have side surfaces facing each other, an isolation pattern disposed between the first and second active regions, a semiconductor extension layer disposed between the first and second active regions, a first source/drain semiconductor layer disposed on the first active region, and a second source/drain semiconductor layer disposed on the second active region. The facing side surfaces of the first and second active regions are closer to the semiconductor extension layer than the isolation pattern.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a field insulating layer disposed on a semiconductor substrate;
a first active region and a second active region, which are disposed in the semiconductor substrate and pass through the field insulating layer;
a semiconductor extension layer disposed between the first and second active regions;
an isolation pattern disposed on the semiconductor extension layer and configured to extend into the field insulating layer;
a first source/drain semiconductor layer disposed on the first active region; and
a second source/drain semiconductor layer disposed on the second active region,
wherein the semiconductor extension layer is disposed between the first active region and the isolation pattern and between the second active region and the isolation pattern.

2. The semiconductor device of claim 1 , wherein the first active region has a line shape, which extends in a first direction; and
a width of the first active region in a second direction perpendicular to the first direction is less than a width of the semiconductor extension layer in the second direction.

3. The semiconductor device of claim 1 , wherein the first and second active regions pass through the field insulating layer and protrude from an upper portion of the field insulating layer.

4. The semiconductor device of claim 1 , further comprising:
a first gate pattern disposed on the first active region;
a second gate pattern disposed on the second active region; and
a dummy gate pattern disposed between the first and second gate patterns,
wherein the dummy gate pattern extends between the first and second active regions and overlaps the isolation pattern.

5. The semiconductor device of claim 4 , wherein the semiconductor extension layer includes portions interposed between the first source/drain semiconductor layer and the dummy gate pattern and between the second source/drain semiconductor layer and the dummy gate pattern.

6. The semiconductor device of claim 1 , wherein the semiconductor extension layer is in contact with the side surfaces of the first and second active regions.

7. The semiconductor device of claim 1 , wherein a level of an upper end of the semiconductor extension layer is higher than a level of an upper surface of the isolation pattern relative to the semiconductor substrate.

8. The semiconductor device of claim 1 , wherein the semiconductor extension layer extends under the isolation pattern relative to the semiconductor substrate.

9. The semiconductor device of claim 1 , wherein the first source/drain semiconductor layer is disposed in a first recessed area in the first active region.

10. The semiconductor device of claim 9 , wherein a level of an upper end of the semiconductor extension layer is higher than a level of a bottom of the first recessed area relative to the semiconductor substrate.

11. The semiconductor device of claim 9 , wherein a level of a bottom of the semiconductor extension layer is lower than a level of a bottom of the first recessed area relative to the semiconductor substrate.

12. The semiconductor device of claim 1 , wherein the facing side surfaces of the first and second active regions are closer to the semiconductor extension layer than the isolation pattern.

13. A semiconductor device, comprising:
a field insulating layer disposed on a semiconductor substrate;
a first active region and a second active region, which pass through the field insulating layer and protrude from an upper portion of the field insulating layer;
a field trench area disposed between the first and second active regions;
a semiconductor extension layer disposed in the field trench area; and
an isolation pattern disposed on the semiconductor extension layer and configured to extend into the field insulating layer.

14. The semiconductor device of claim 13 , wherein the semiconductor extension layer has a “U” shape.

15. The semiconductor device of claim 13 , wherein a bottom of the isolation pattern is not coplanar with a bottom of the field insulating layer.

16. The semiconductor device of claim 13 , wherein a level of a bottom of the isolation pattern is higher than a level of a bottom of the field insulating layer relative to the semiconductor substrate.

17. The semiconductor device of claim 13 , further comprising:
a first source/drain semiconductor layer disposed in a first recessed area in the first active region;
a second source/drain semiconductor layer disposed in a second recessed area in the second active region;
a first gate pattern configured to overlap the first active region;
a second gate pattern configured to overlap the second active region; and
a dummy gate pattern configured to overlap the isolation pattern.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Sungmin
• Kang Jisu
• Park Jaehyun
• Shin Heonjong
• Lee Yuri

Classifications

• H10D84/0158

  the components including FinFETs · CPC title

• H10D84/0151

  Manufacturing their isolation regions · CPC title

• H10D84/83

  of only insulated-gate FETs [IGFET] · CPC title

• H10D84/038

  using silicon technology, e.g. SiGe · CPC title

• H10D62/292

  Non-planar channels of IGFETs (resulting from the gate electrode dispositions, e.g. within trenches H10D64/512) · CPC title