Nonvolatile memory package, storage device including the same, and method of operating thereof

Patent metadata

Field	Value
Publication number	US-12462857-B2
Application number	US-202318529619-A
Country	US
Kind code	B2
Filing date	Dec 5, 2023
Priority date	Mar 14, 2023
Publication date	Nov 4, 2025
Grant date	Nov 4, 2025

Abstract

A storage device includes a plurality of memory chips, a buffer chip connected to the plurality of memory chips, and a controller connected to the buffer chip. The buffer chip is configured to periodically receive a first command from the controller, and perform a DQS oscillator enable operation in response to the first command. At least one memory chip among the plurality of memory chips and the buffer chip are configured to perform write training or read training when the DQS oscillator enable operation is performed.

First claim

What is claimed is:

1 . A storage device comprising:
a plurality of memory chips; a buffer chip connected to the plurality of memory chips; and a controller connected to the buffer chip, wherein the buffer chip is configured to periodically receive a first command from the controller, and perform a DQS oscillator enable operation in response to the first command, and at least one memory chip among the plurality of memory chips and the buffer chip are configured to perform write training or read training when the DQS oscillator enable operation is performed.

2 . The storage device of claim 1 , wherein the write training and the read training are performed using a DQS oscillator clock generated by the buffer chip or by the at least one memory chip.

3 . The storage device of claim 1 , wherein, in the write training, a DQS oscillator of the buffer chip is configured to generate a DQS oscillator clock to perform the write training.

4 . The storage device of claim 3 , wherein the buffer chip is configured to transmit test data to the at least one memory chip using the DQS oscillator clock as a strobe clock DQS.

5 . The storage device of claim 4 , wherein, in the write training, the at least one memory chip is configured to align phases of the test data and the strobe clock DQS by sampling the test data in response to the strobe clock DQS, comparing the sampled data with expected data, determining a pass/failure result according to a result of the comparison, and controlling at least one delay chain according to the determined pass/failure result.

6 . The storage device of claim 1 , wherein, in the read training, the at least one memory chip, among the plurality of memory chips, is configured to generate a DQS oscillator clock to perform the read training.

7 . The storage device of claim 6 , wherein the at least one memory chip is configured to transmit test data to the buffer chip using the DQS oscillator clock as a strobe clock DQS.

8 . The storage device of claim 7 , wherein, in the read training, the buffer chip is configured to align phases of the test data and the strobe clock DQS by sampling the test data in response to the strobe clock DQS, comparing the sampled data with expected data, determining a pass/failure according to a result of the comparison, and controlling at least one delay chain according to the determined pass/failure.

9 . The storage device of claim 1 , wherein the write training and the read training are configured to sample N−1-th and N-th test data in synchronization with a strobe clock DQS, output a first pass/failure result by comparing the sampled test data with N−1-th expected data, output a second pass/failure result by comparing the sampled test data with N-th expected data, generate a first sweep code corresponding to a conversion count value of the first pass/failure result, generate a second sweep code corresponding to a conversion count value of the second pass/failure result, and output a lock code of the strobe clock DQS using the first sweep code and the second sweep code.

10 . The storage device of claim 1 , wherein the write training and the read training are configured to perform first sampling on N-th test data to generate first sampled test data in synchronization with a rising edge of a strobe clock DQS, perform second sampling on N+1-th test data to generate second sampled test data in synchronization with a falling edge of the strobe clock DQS, output a first pass/failure result by comparing the first sampled test data with N-th expected data, output a second pass/failure result by comparing the second sampled test data with the N-th expected data, generate a first sweep code corresponding to each of a conversion count value of the first pass/failure result and a conversion count value of the second pass/failure result, generate a second sweep code corresponding to each of the conversion count value of the first pass/failure result and the conversion count value of the second pass/failure result, and output a lock code of the strobe clock DQS using the first sweep code and the second sweep code.

11 . A method of operating a storage device, the method comprising:
performing a DQS oscillator enable/disable operation between a controller and a buffer chip; and performing training between a memory chip and the buffer chip using a DQS oscillator clock generated by a DQS oscillator of the buffer chip or the memory chip while performing the DQS oscillator enable/disable operation.

12 . The method of claim 11 , wherein the performing the DQS oscillator enable/disable operation includes:
receiving a first command from the controller; and enabling the DQS oscillator in response to the first command.

13 . The method of claim 11 , wherein the performing the training includes:
generating, by a DQS oscillator of the memory chip, a DQS oscillator clock; transmitting, by the memory chip, test data to the buffer chip using the DQS oscillator clock as a strobe clock DQS; and aligning phases of the test data and the strobe clock DQS by sampling, by the buffer chip, the test data in response to the strobe clock DQS, comparing the sampled data with expected data, determining a pass/failure result according to a result of the comparison, and controlling at least one delay chain according to the determined pass/failure result.

14 . The method of claim 11 , wherein the performing the training includes:
generating, by a DQS oscillator of the buffer chip, a DQS oscillator clock; transmitting, by the buffer chip, test data to the memory chip using the DQS oscillator clock as a strobe clock DQS; and aligning phases of the test data and the strobe clock DQS by sampling, by the memory chip, the test data in response to the strobe clock DQS, comparing the sampled data with expected data, determining a pass/failure result according to a result of the comparison, and controlling at least one delay chain according to the determined pass/failure result.

15 . The method of claim 11 , further comprising storing a lock code according to the training.

16 . A nonvolatile memory package comprising:
a plurality of memory chips; and a buffer chip connected to the plurality of memory chips, wherein the buffer chip includes:
a first sampler configured to sample read data transmitted from one of the plurality of memory chips when a read operation is performed;
a second sampler configured to sample write data transmitted from an external device when a program operation is performed;
a DQS oscillator configured to generate a strobe clock DQS in response to a first command; and
a counter and register configured to count the strobe clock DQS and store a counted value, and
wherein when the DQS oscillator is enabled in response to the first command, the buffer chip and at least one of the plurality of memory chips perform hidden read training or hidden write training.

17 . The nonvolatile memory package of claim 16 , wherein, in the hidden read training, each of the plurality of memory chips includes:
a register configured to store test data; a first DQS oscillator configured to generate a first strobe clock DQS; and a first counter and register configured to count the first strobe clock DQS and store a counted value.

18 . The nonvolatile memory package of claim 17 , wherein the buffer chip includes:
a first delay chain configured to delay, using a delay code, the test data received from one memory chip among the plurality of memory chips in the read training; a second delay chain configured to dela

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kavala Anil
• Jo Youngmin
• Park Jungjune
• Yoon Chiweon

Classifications

• G11C16/32 Primary

  Timing circuits · CPC title

• G11C7/222

  Clock generating, synchronizing or distributing circuits within memory device · CPC title

• G06F3/0679

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title

• G06F3/061

  Improving I/O performance · CPC title

• G11C16/10

  Programming or data input circuits · CPC title